Microchip Technology AC244055 Data Sheet
2011-2013 Microchip Technology Inc.
DS40001574C-page 185
PIC16(L)F1938/9
20.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
• TMR0 can be used to gate Timer1
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
• TMR0 can be used to gate Timer1
is a block diagram of the Timer0 module.
20.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
or an 8-bit counter.
20.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
two instruction cycles immediately following the write.
20.1.2
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSCLK) signal.
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’ and resetting the T0XCS bit in the CPSCON0 register
to ‘0’.
8-Bit Counter mode using the Capacitive Sensing
Oscillator (CPSCLK) signal is selected by setting the
TMR0CS bit in the OPTION_REG register to ‘1’ and
setting the T0XCS bit in the CPSCON0 register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
on every rising or falling edge of the T0CKI pin or the
Capacitive Sensing Oscillator (CPSCLK) signal.
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’ and resetting the T0XCS bit in the CPSCON0 register
to ‘0’.
8-Bit Counter mode using the Capacitive Sensing
Oscillator (CPSCLK) signal is selected by setting the
TMR0CS bit in the OPTION_REG register to ‘1’ and
setting the T0XCS bit in the CPSCON0 register to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
FIGURE 20-1:
BLOCK DIAGRAM OF THE TIMER0
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
T0CKI
TMR0SE
TMR0
PS<2:0>
Data Bus
Set Flag bit TMR0IF
on Overflow
TMR0CS
0
1
0
1
8
8
8-bit
Prescaler
F
OSC
/4
PSA
Sync
2 T
CY
Overflow to Timer1
1
0
CPSCLK
T0XCS