Microchip Technology MCP7383XRD-PPM Data Sheet

Page of 32
© 2009 Microchip Technology Inc.
DS22005B-page 11
MCP73833/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in 
.
TABLE 3-1:
PIN FUNCTION TABLE
3.1
Battery Management Input Supply 
(V
DD
)
A supply voltage of [V
REG 
(typical) + 0.3V] to 6V is 
recommended. Bypass to V
SS
 with a minimum of 1 µF.
3.2
Charge Status Outputs (STAT1, 
STAT2)
STAT1 and STAT2 are open-drain logic outputs for con-
nection to a LED for charge status indication.
Alternatively, a pull-up resistor can be applied for
interfacing to a host microcontroller.
3.3
Battery Management 0V Reference 
(V
SS
)
Connect to negative terminal of battery and input
supply.
3.4
Current Regulation Set (PROG)
Preconditioning, fast charge, and termination currents
are scaled by placing a resistor from PROG to V
SS
.
The charge management controller can be disabled by
allowing the PROG input to float.
3.5
Power Good Indication (PG) 
MCP73833 Only
The power good (PG) option is a pseudo open-drain
output. The PG output can sink current, but not source
current. However, there is a diode path back to the
input, and, as such, the PG output should only be
pulled up to the input. The PG output is low whenever
the input to the MCP73833 is above the UVLO
threshold and greater than the battery voltage.
3.6
Timer Enable Input (TE)  
MCP73834 Only
The timer enable (TE) input option is used to enable or
disable the internal timer. A low signal on this pin
enables the internal timer and a high signal disables
the internal timer. The TE input can be used to disable
the timer when the charger is supplying current to
charge the battery and power the system load. The TE
input is compatible with 1.8V logic.
3.7
Thermistor Input (THERM)
An internal 50 µA current source provides the bias for
most common 10 k
Ω negative-temperature coefficient
thermistors (NTC). The MCP73833/4 compares the
voltage at the THERM pin to factory set thersholds of
1.20V and 0.25V, typically.
3.8
Battery Charge Control Output 
(V
BAT
)
Connect to positive terminal of battery. Drain terminal
of internal P-channel MOSFET pass transistor. Bypass
to V
SS
 with a minimum of 1 µF to ensure loop stability
when the battery is disconnected.
3.9
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the V
SS
 pin; they must
be connected to the same potential.
Pin No.
Symbol
Function
DFN-10
MSOP-10
1
1
V
DD
Battery Management Input Supply
2
2
V
DD
Battery Management Input Supply
3
3
STAT1
Charge Status Output
4
4
STAT2
Charge Status Output
5
5
V
SS
Battery Management 0V Reference
6
6
PROG
Current Regulation Set and Charge Control Enable
7
7
PG, TE
MCP73833: Power Good output, MCP73834: Timer Enable input
8
8
THERM
Thermistor input
9
9
V
BAT
Battery Charge Control Output
10
10
V
BAT
Battery Charge Control Output
11
EP
Exposed Thermal Pad (EP); must be connected to V
SS
.