Microchip Technology MA320001 Data Sheet
© 2011 Microchip Technology Inc.
DS61143H-page 101
PIC32MX3XX/4XX
12.0
I/O PORTS
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC
als. They allow the PIC
®
MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
• Individual Output Pin Open-drain Enable/Disable
• Individual Input Pin Weak Pull-up Enable/Disable
• Monitor Selective Inputs and Generate Interrupt
• Individual Input Pin Weak Pull-up Enable/Disable
• Monitor Selective Inputs and Generate Interrupt
when Change in Pin State is Detected
• Operation during CPU Sleep and Idle modes
• Fast Bit Manipulation using CLR, SET and INV
• Fast Bit Manipulation using CLR, SET and INV
Registers
illustrates a block diagram of a typical
multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) of the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) of the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(
www.microchip.com/PIC32
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Peripheral Output Data
Peripheral Module
Peripheral Output Enable
PIO Module
Peripheral Module Enable
WR LAT
I/O Pin
WR PORT
Data Bus
RD LAT
RD PORT
RD TRIS
WR TRIS
0
1
RD ODC
SYS
CLK
Q
D
CK
EN Q
Q
D
CK
EN Q
Q
D
CK
EN Q
Q
D
CK
Q
Q
D
CK
Q
0
1
SYS
CLK
WR ODC
ODC
TRIS
LAT
Sleep
1
0
1
0
Output Multiplexers
I/O Cell
Synchronization
R
Peripheral Input
Legend:
R = Peripheral input buffer types may vary. Refer to
for peripheral details.
Note:
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
for any specific port/peripheral combination may be different than it is shown here.
Peripheral Input Buffer