Microchip Technology MA320001 Data Sheet
© 2011 Microchip Technology Inc.
DS61143H-page 165
PIC32MX3XX/4XX
FIGURE 29-4:
POWER-ON RESET TIMING CHARACTERISTICS
V
DD
V
POR
Note 1: The Power-up period will be extended if the power-up sequence completes before the device
exits from BOR (V
DD
< V
DDMIN
).
2: Includes interval voltage regulator stabilization delay.
3: Power-up Timer (PWRT); only active when the internal voltage regulator is disabled.
SY00
Power Up Sequence
(Note 2)
(Note 2)
V
DD
V
POR
V
CORE
External V
CORE
Provided
Internal Voltage Regulator Enabled
(T
PU
)
SY10
SY01
Power Up Sequence
(Note 3)
CPU starts fetching code
CPU starts fetching code
(T
PWRT
)
Clock Sources = (HS, HSPLL, XT, XTPLL and S
OSC
)
V
DD
V
POR
SY00
Power Up Sequence
(Note 2)
(Note 2)
Internal Voltage Regulator Enabled
(T
PU
)
(T
SYSDLY
)
CPU starts fetching code
(Note 1)
(Note 1)
(Note 1)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
(T
OST
)
SY02
(T
SYSDLY
)
SY02
(T
SYSDLY
)
SY02