Microchip Technology MA320001 Data Sheet

© 2011 Microchip Technology Inc.

DS61143H-page 43

PIC32MX3XX/4XX microcontrollers provide 4 GB of
unified virtual memory address space. All memory
regions including program, data memory, SFRs and
Configuration registers reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX3XX/4XX to
execute from data memory.

• 32-bit native data width

• Separate User and Kernel mode address space

• Flexible program Flash memory partitioning

• Flexible data RAM partitioning for data and 

program space

• Separate boot Flash memory for protected code

• Robust bus exception handling to intercept 

runaway code

• Simple memory mapping with Fixed Mapping 

Translation (FMT) unit

• Cacheable and non-cacheable address regions

PIC32MX3XX/4XX microcontrollers implement two
address spaces: Virtual and Physical. All hardware
resources such as program memory, data memory and
peripherals are located at their respective physical
addresses. Virtual addresses are exclusively used by
the CPU to fetch and execute instructions as well as
access peripherals. Physical addresses are used by
peripherals such as DMA and Flash controller that
access memory independently of CPU.

Note 1: This data sheet summarizes the features

of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 3. “Memory
Organization” (DS61115) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(

www.microchip.com/PIC32

).