Microchip Technology MA320001 Data Sheet

PIC32MX3XX/4XX

DS61143H

-page 64

2011 Microchip T

chnolo

y Inc.

TABLE 4-14:

DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY

irtual Address

(BF88_#

)

Regis

ter

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

3000 DMACON

(1)

31:16

—

0000

15:0

—

SIDL

SUSPEND

—

0000

3010

DMASTAT

31:16

—

0000

15:0

—

RDWR

—

DMACH<1:0>

0000

3020 DMAADDR

31:16

DMAADDR<31:0>

0000

15:0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more information.

TABLE 4-15:

DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY

(1)

irtual Ad

dress

(BF88_

Regi

ster

Bit

Range

Bits

All

Reset

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

3030 DCRCCON

31:16

—

0000

15:0

—

PLEN<3:0>

CRCEN

CRCAPP

—

CRCCH<1:0>

0000

3040 DCRCDATA

31:16

—

0000

15:0

DCRCDATA<15:0>

0000

3050 DCRCXOR

31:16

—

0000

15:0

DCRCXOR<15:0>

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.