Microchip Technology MA320001 Data Sheet

2011 Micr

och

ip T
e

chn

logy Inc.

1143H-p

age 73

PIC32MX3XX/4XX

TABLE 4-27:

PORTE REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

Reset

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6100

TRISE

31:16

—

0000

15:0

—

TRISE9

TRISE8

TRISE7

TRISE6

TRISE5

TRISE4

TRISE3

TRISE2

TRISE1

TRISE0

03FF

6110

PORTE

31:16

—

0000

15:0

—

RE9

RE8

RE7

RE6

RE5

RE4

RE3

RE2

RE1

RE0

xxxx

6120

LATE

31:16

—

0000

15:0

—

LATE9

LATE8

LATE7

LATE6

LATE5

LATE4

LATE3

LATE2

LATE1

LATE0

xxxx

6130

ODCE

31:16

—

0000

15:0

—

ODCE9

ODCE8

ODCE7

ODCE6

ODCE5

ODCE4

ODCE3

ODCE2

ODCE1

ODCE0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.

TABLE 4-28:

PORTE REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H
DEVICES ONLY

(1)

irtual Address

(BF88_#

)

Regis

ter

Name

it Range

Bits

All Re

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6100

TRISE

31:16

—

0000

15:0

—

TRISE7

TRISE6

TRISE5

TRISE4

TRISE3

TRISE2

TRISE1

TRISE0

00FF

6110

PORTE

31:16

—

0000

15:0

—

RE7

RE6

RE5

RE4

RE3

RE2

RE1

RE0

xxxx

6120

LATE

31:16

—

0000

15:0

—

LATE7

LATE6

LATE5

LATE4

LATE3

LATE2

LATE1

LATE0

xxxx

6130

ODCE

31:16

—

0000

15:0

—

ODCE7

ODCE6

ODCE5

ODCE4

ODCE3

ODCE2

ODCE1

ODCE0

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.