Microchip Technology MA320001 Data Sheet

2011 Micr

och

ip T
e

chn

logy Inc.

1143H-p

age 77

PIC32MX3XX/4XX

TABLE 4-35:

CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L,
PIC32MX360F512L, PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY

(1)

irtual A

ddress

(BF88_#

)

Regis

ter

Bit Range

Bits

All

Reset

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

61C0

CNCON

31:16

—

0000

15:0

—

SIDL

—

0000

61D0

CNEN

31:16

—

CNEN21

CNEN20

CNEN19

CNEN18

CNEN17

CNEN16

0000

15:0

CNEN15

CNEN14

CNEN13

CNEN12

CNEN11

CNEN10

CNEN9

CNEN8

CNEN7

CNEN6

CNEN5

CNEN4

CNEN3

CNEN2

CNEN1

CNEN0

0000

61E0

CNPUE

31:16

—

CNPUE21

CNPUE20

CNPUE19

CNPUE18 CNPUE17 CNPUE16 0000

15:0

CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10

CNPUE9

CNPUE8

CNPUE7

CNPUE6

CNPUE5

CNPUE4

CNPUE3

CNPUE2

CNPUE1

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.

TABLE 4-36:

CHANGE NOTICE AND PULL-UP REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H,
PIC32MX340F128H, PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H
AND PIC32MX440F512H DEVICES ONLY

(1)

irtual Ad

dress

(BF88_

Regi

ster

Nam

Bit

Range

Bits

All

Reset

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

61C0

CNCON

31:16

—

0000

15:0

—

SIDL

—

0000

61D0

CNEN

31:16

—

CNEN18

CNEN17

CNEN16

0000

15:0

CNEN15

CNEN14

CNEN13

CNEN12

CNEN11

CNEN10

CNEN9

CNEN8

CNEN7

CNEN6

CNEN5

CNEN4

CNEN3

CNEN2

CNEN1

CNEN0

0000

61E0

CNPUE

31:16

—

CNPUE18 CNPUE17 CNPUE16 0000

15:0

CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10

CNPUE9

CNPUE8

CNPUE7

CNPUE6

CNPUE5

CNPUE4

CNPUE3

CNPUE2

CNPUE1

0000

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more

information.