Microchip Technology MCP3421DM-WS Data Sheet

© 2009 Microchip Technology Inc.

DS22003E-page 3

V

DD

...................................................................................7.0V

All inputs and outputs w.r.t V

SS 

............... –0.3V to V

DD

+0.3V

Differential Input Voltage  ...................................... |V

DD

 - V

SS

|

Output Short Circuit Current  ................................ Continuous

Current at Input Pins  ....................................................±2 mA

Current at Output and Supply Pins  ............................±10 mA

Storage Temperature ....................................-65°C to +150°C

Ambient Temp. with power applied ...............-55°C to +125°C

ESD protection on all pins 

................ ≥ 6 kV HBM, ≥ 400V MM

Maximum Junction Temperature (T

J

) . .........................+150°C

†Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability

.

Electrical Specifications: Unless otherwise specified, all parameters apply for T

A

 = -40°C to +85°C, V

DD

 = +5.0V, V

SS

 = 0V,

V

IN

+ = V

IN

- = V

REF

/2. All ppm units use 2*V

REF

 as full scale range.

Differential Input Range

—

±2.048/PGA

—

V

V

IN

 = V

IN

+ - V

IN

-

Common-Mode Voltage Range 
(absolute) 

V

SS

-0.3

—

V

DD

+0.3

V

Differential Input Impedance 
(Note 2)

Z

IND

 (f)

—

2.25/PGA

—

M

Ω

During normal mode operation

Common Mode input 
Impedance

Z

INC

 (f)

—

25

—

M

Ω

PGA = 1, 2, 4, 8

Resolution and No Missing 
Codes 

12

—

—

Bits

DR = 240 SPS

14

—

—

Bits

DR = 60 SPS

16

—

—

Bits

DR = 15 SPS

18

—

—

Bits

DR = 3.75 SPS

Data Rate

DR

176

240

328

SPS

S1,S0 = ‘00’, (12 bits mode)

44

60

82

SPS

S1,S0 = ‘01’, (14 bits mode)

11

15

20.5

SPS

S1,S0 = ‘10’, (16 bits mode)

2.75

3.75

5.1

SPS

S1,S0 = ‘11’, (18 bits mode)

Output Noise

—

1.5

—

µV

RMS

T

A

 = +25°C, DR = 3.75 SPS, 

PGA = 1, V

IN

 = 0 

Integral Nonlinearity

 (Note 4)

INL

—

10

35

ppm of

FSR

DR = 3.75 SPS
(Note 6)

Internal Reference Voltage

V

REF

—

2.048

—

V

Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.

This input impedance is due to 3.2 pF internal input sampling capacitor. 

The total conversion speed includes auto-calibration of offset and gain.

INL is the difference between the endpoints line and the measured code at the center of the quantization band.

Includes all errors from on-board PGA and V

REF

.

Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.

This parameter is ensured by characterization and not 100% tested.

This parameter is ensured by design and not 100% tested.