Microchip Technology MCP3421DM-WS Data Sheet

DS22093B-page 24

© 2008 Microchip Technology Inc.

4.3.1

INPUT OFFSET VOLTAGE OVER 
TEMPERATURE

 gives both the linear and quadratic tempera-

ture coefficients (TC

1

 and TC

2

) of input offset voltage.

The input offset voltage, at any temperature in the
specified range, can be calculated as follows:

4.3.2

DC GAIN PLOTS

 and 

 are histograms

of the reciprocals (in units of µV/V) of CMRR, PSRR
and A

OL

, respectively. They represent the change in

input offset voltage (V

OS

) with a change in common

mode input voltage (V

CM

), power supply voltage (V

DD

)

and output voltage (V

OUT

).

The 1/A

OL

 histogram is centered near 0 µV/V because

the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise, not unstable behavior. We validate the op amps’
stability by making multiple measurements of V

OS

;

instability would manifest itself as a greater unex-
plained variability in V

OS

 or as the railing of the output.

4.3.3

SOURCE RESISTANCES

The input bias currents have two significant
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10

Ω

to 1 k

Ω at high frequencies (i.e., above 1 MHz). This

helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.

4.3.4

SOURCE CAPACITANCE

The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match.

4.3.5

CAPACITIVE LOADS

Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These auto-zeroed op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (R

ISO

 in 

improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher frequen-
cies. The bandwidth will be generally lower than the
bandwidth with no capacitive load.

 gives recommended R

ISO

 values for

different capacitive loads and is independent of the
gain.

( )

1

ΔT TC

2

ΔT

2

+

+

=

Where:

ΔT

=

T

A

– 25°C

V

OS

(T

A

)

=

input offset voltage at T

A

V

OS

=

input offset voltage at +25°C

TC

1

=

linear temperature coefficient

TC

2

=

quadratic temperature 
coefficient

R

ISO

C

L

V

OUT