Microchip Technology MA180023 Data Sheet
2011 Microchip Technology Inc.
DS39932D-page 487
PIC18F46J11 FAMILY
TABLE 29-9:
EXTERNAL CLOCK TIMING REQUIREMENTS
TABLE 29-10: PLL CLOCK TIMING SPECIFICATIONS
TABLE 29-11: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
1A
F
OSC
External CLKI Frequency
(1)
DC
48
MHz
EC Oscillator mode
4
12
ECPLL Oscillator mode
Oscillator Frequency
(1)
4
16
MHz
HS Oscillator mode
4
12
HSPLL Oscillator mode
1
T
OSC
External CLKI Period
(1)
20.8
—
ns
EC Oscillator mode
83.3
—
ECPLL Oscillator mode
Oscillator Period
(1)
62.5
250
ns
HS Oscillator mode
83.3
250
HSPLL Oscillator mode
2
T
CY
Instruction Cycle Time
(1)
83.3
DC
ns
T
CY
= 4/F
OSC
, Industrial
3
T
OS
L,
T
OS
H
External Clock in (OSC1)
High or Low Time
High or Low Time
10
—
ns
EC Oscillator mode
4
T
OS
R,
T
OS
F
External Clock in (OSC1)
Rise or Fall Time
Rise or Fall Time
—
7.5
ns
EC Oscillator mode
Note 1:
Instruction cycle period (T
CY
) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
F10
F
PLLIN
PLL Input Frequency Range
4
—
12
MHz
F11
F
PLLO
PLL Output Frequency (4x F
PLLIN
)
16
—
48
MHz
F12
t
rc
PLL Start-up Time (lock time)
—
—
2
ms
† Data in “Typ” column is at 3.3V, 25
C, unless otherwise stated.
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz,
4 MHz,
2 MHz,
1 MHz,
500 kHz,
250 kHz,
125 kHz,
31 kHz
(1)
All Devices
-1
+/-0.15
+1
%
0°C to +85°C
V
DD
= 2.0-3.3V
-1
+/-0.25
+1
%
-40°C to +85°C
V
DD
= 2.0-3.6V,
V
DDCORE
= 2.0-2.7V
INTRC Accuracy @ Freq = 31 kHz
(1)
All Devices
20.3
—
42.2
kHz
-40°C to +85°C
V
DD
= 2.0-3.6V,
V
DDCORE
= 2.0-2.7V
Note 1:
The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given time.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.
When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’, use
the INTRC accuracy specification.