Microchip Technology ARD00354 Data Sheet
MCP6N11
DS25073A-page 30
© 2011 Microchip Technology Inc.
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below V
to go more than one diode drop below V
SS
. They also
clamp any voltages that go too far above V
DD
; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
overvoltage (beyond V
operation, but not low enough to protect against slow
overvoltage (beyond V
DD
) events. Very fast ESD
events (that meet the spec) are limited so that damage
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
does not occur.
In some applications, it may be necessary to prevent
excessive voltages from reaching the op amp inputs.
shows one approach to protecting these
inputs. D
1
and D
2
may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or diode-
connected FETs for low leakage.
connected FETs for low leakage.
FIGURE 4-5:
Protecting the Analog Inputs
Against High Voltages.
4.2.1.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see
of these amplifiers, the circuit must limit the currents
into the input pins (see
). This requirement is independent of
the voltage limits previously discussed.
shows one approach to protecting these
inputs. The resistors R
1
and R
2
limit the possible
current in or out of the input pins (and into D
1
and D
2
).
The diode currents will dump onto V
DD
.
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of the
resistor R
resistor R
1
and R
2
. In this case, the currents through
the diodes D
1
and D
2
need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (V
limiters; the DC current into the input pins (V
IP
and V
IM
)
should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (V
CM
) is below ground (V
SS
); see
4.2.1.4
Input Voltage Ranges
shows possible input voltage values
(V
SS
= 0V). Lines with a slope of +1 have constant V
DM
(e.g., the V
DM
= 0 line). Lines with a slope of -1 have
constant V
CM
(e.g., the V
CM
= V
DD
/2 line).
For normal operation, V
IP
and V
IM
must be kept within
the region surrounded by the thick blue lines. The
horizontal and vertical blue lines show the limits on the
individual inputs. The blue lines with a slope of +1 show
the limits on V
horizontal and vertical blue lines show the limits on the
individual inputs. The blue lines with a slope of +1 show
the limits on V
DM
; the larger G
MIN
is, the closer they are
to the V
DM
= 0 line.
The input voltage range specs (V
IVL
and V
IVH
) change
with the supply voltages (V
SS
and V
DD
, respectively).
The differential input range specs (V
DML
and V
DMH
)
change with minimum gain (G
MIN
). Temperature also
affects these specs.
To take full advantage of V
To take full advantage of V
DML
and V
DMH
, set V
REF
(see
) so that the output
(V
OUT
) is centered between the supplies (V
SS
and
V
DD
).
FIGURE 4-7:
Input Voltage Ranges.
V
DD
V
1
D
1
V
2
D
2
U
1
MCP6N11
min(R
1
, R
2
) >
V
SS
– min(V
1
, V
2
)
2 mA
V
DD
V
1
R
1
D
1
V
2
R
2
D
2
U
1
MCP6N11
min(R
1
, R
2
)
>
max(V
1
, V
2
) – V
DD
2 mA
V
IP
V
IM
V
DM
=
0
V
IVH
V
IVL
0
V
IV
H
V
IV
L
0
V
DM
=
V
DM
H
V
CM
=
V
DD
/2
V
DM
=
V
DM
H
V
DD
V
DD