Microchip Technology DM164130-10 User Manual
PSMC Designer User’s Guide
DS40001671B-page 36
2012-2013 Microchip Technology Inc.
FIGURE 2-25:
AUTO-SHUTDOWN
2.22 SYNC OUTPUT CONTROL (NOT AVAILABLE ON THE PIC16(L)F1782/3)
. The sync output of
PIC16(L)F1783/3 devices is fixed to the period event output. All other devices can
select either the period event or rising event as the sync output.
The sync output control, shown in
select either the period event or rising event as the sync output.
The sync output control, shown in
, is opened by clicking on the sync block
of the main GUI. The synchronization signal output to other PSMC sync inputs may
come directly from the period event or from the rising edge event. Clicking on the
double-pole switch selects between the two possibilities.
When the switch selects the period event as the master PSMC sync source then all
slave PSMCs will synchronize their period events to the master. This requires the
period time for all slave PSMCs to be as long as or longer than the period time of the
master.
When the switch selects the rising event as the master PSMC sync source, then the
master PSMC rising event defaults to the master PSMC period event, and the slave
PSMCs period is delayed by the master PSMC rising event time. Delaying slaves in this
manner retains the 0 to 100% duty cycle range of the master and slave in phase
delayed applications.
come directly from the period event or from the rising edge event. Clicking on the
double-pole switch selects between the two possibilities.
When the switch selects the period event as the master PSMC sync source then all
slave PSMCs will synchronize their period events to the master. This requires the
period time for all slave PSMCs to be as long as or longer than the period time of the
master.
When the switch selects the rising event as the master PSMC sync source, then the
master PSMC rising event defaults to the master PSMC period event, and the slave
PSMCs period is delayed by the master PSMC rising event time. Delaying slaves in this
manner retains the 0 to 100% duty cycle range of the master and slave in phase
delayed applications.
FIGURE 2-26:
SYNC CONTROL