Microchip Technology MA240017 Data Sheet

DS39927C-page 102

 2008-2011 Microchip Technology Inc.

10.2.2

IDLE MODE

Idle mode has these features:
• The CPU will stop executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By 

default, all peripheral modules continue to operate 
normally from the system clock source, but can 
also be selectively disabled (see 

). 

• If the WDT or FSCM is enabled, the LPRC will 

also remain active.

The device will wake from Idle mode on any of these
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately,
starting with the instruction following the PWRSAV
instruction or the first instruction in the ISR.

10.2.3

INTERRUPTS COINCIDENT WITH 
POWER SAVE INSTRUCTIONS

Any interrupt that coincides with the execution of a
PWRSAV

 instruction will be held off until entry into Sleep

or Idle mode has completed. The device will then
wake-up from Sleep or Idle mode.

10.2.4

DEEP SLEEP MODE

In PIC24F16KA102 family devices, Deep Sleep mode
is intended to provide the lowest levels of power con-
sumption available without requiring the use of external
switches to completely remove all power from the
device. Entry into Deep Sleep mode is completely
under software control. Exit from Deep Sleep mode can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out
In Deep Sleep mode, it is possible to keep the device
Real-Time Clock and Calendar (RTCC) running without
the loss of clock cycles.

The device has a dedicated Deep Sleep Brown-out
Reset (DSBOR) and a Deep Sleep Watchdog Timer
Reset (DSWDT) for monitoring voltage and time-out
events. The DSBOR and DSWDT are independent of
the standard BOR and WDT used with other
power-managed modes (Sleep, Idle and Doze).

10.2.4.1

Entering Deep Sleep Mode

Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command (PWRSAV  #SLEEP_MODE), within one
instruction cycle, to minimize the chance that Deep
Sleep will be spuriously entered. 
If the PWRSAV command is not given within one instruc-
tion cycle, the DSEN bit will be cleared by the hardware
and must be set again by the software before entering
Deep Sleep mode. The DSEN bit is also automatically
cleared when exiting the Deep Sleep mode. 

The sequence to enter Deep Sleep mode is:
1.

If the application requires the Deep Sleep WDT,
enable it and configure its clock source (see

 for

details).

2.

If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).

3.

If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module (see 

 for more

information). 

4.

If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).

5.

Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>).

6.

Enter Deep Sleep mode by issuing 3 NOP
commands, and then a PWRSAV #0 instruction.

Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.

To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T

CY

after clearing the RELEASE bit.