Microchip Technology MA240017 Data Sheet

DS39927C-page 114

 2008-2011 Microchip Technology Inc.

11.1.1

OPEN-DRAIN CONFIGURATION

In addition to the PORT, LAT and TRIS registers for
data control, each port pin can also be individually
configured for either digital or open-drain output. This is
controlled by the Open-Drain Control register, ODCx,
associated with each port. Setting any of the bits
configures the corresponding pin to act as an
open-drain output. 
The maximum open-drain voltage allowed is the same
as the maximum V

IH

 specification. 

The use of the AD1PCFG and TRIS register controls
the operation of the A/D port pins. The port pins that are
desired as analog inputs must have their
corresponding TRIS bit set (input). If the TRIS bit is
cleared (output), the digital output level (V

OH

 or V

OL

)

will be converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Analog levels on any pin that is defined as a digital
input (including the ANx pins) may cause the input
buffer to consume current that exceeds the device
specifications.

11.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP.

The input change notification function of the I/O ports
allows the PIC24F16KA102 family of devices to
generate interrupt requests to the processor in
response to a Change-of-State (COS) on selected
input pins. This feature is capable of detecting input
Change-of-States even in Sleep mode, when the

clocks are disabled. Depending on the device pin
count, there are up to 23 external signals (CN0 through
CN22) that may be selected (enabled) for generating
an interrupt request on a Change-of-State.
There are six control registers associated with the CN
module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up/pull-down
connected to it. The pull-ups act as a current source
that is connected to the pin and the pull-downs act as a
current sink to eliminate the need for external resistors
when push button or keypad devices are connected.
On any pin, only the pull-up resistor or the pull-down
resistor should be enabled, but not both of them. If the
push button or the keypad is connected to V

DD

, enable

the pull-down, or if they are connected to V

SS

, enable

the pull-up resistors. The pull-ups are enabled
separately using the CNPU1 and CNPU2 registers,
which contain the control bits for each of the CN pins. 
Setting any of the control bits enables the weak
pull-ups for the corresponding pins. The pull-downs are
enabled separately using the CNPD1 and CNPD2
registers, which contain the control bits for each of the
CN pins. Setting any of the control bits enables the
weak pull-downs for the corresponding pins.
When the internal pull-up is selected, the pin uses V

DD

as the pull-up source voltage. When the internal
pull-down is selected, the pins are pulled down to V

SS

by an internal resistor. Make sure that there is no
external pull-up source/pull-down sink when the
internal pull-ups/pull-downs are enabled.

Pull-ups and pull-downs on change
notification pins should always be
disabled whenever the port pin is
configured as a digital output.

MOV

0xFF00, W0;

//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs

MOV

W0, TRISBB; 

NOP;

//Delay 1 cycle

BTSS

PORTB, #13;

//Next Instruction

Equivalent ‘C’ Code   

TRISB = 0xFF00;

//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs

NOP();

//Delay 1 cycle

if(PORTBbits.RB13 == 1)

// execute following code if PORTB pin 13 is set.

{

}