Microchip Technology MA240017 Data Sheet
PIC24F16KA102 FAMILY
DS39927C-page 168
2008-2011 Microchip Technology Inc.
FIGURE 20-2:
CRC GENERATOR RECONFIGURED FOR x
16
+ x
12
+ x
5
+ 1
20.1
User Interface
20.1.1
DATA INTERFACE
To start serial shifting, a value of ‘1’ must be written to
the CRCGO bit.
The module incorporates a FIFO that is 8-level deep
when PLEN<3:0> > 7 and 16-deep, otherwise. The
data for which the CRC is to be calculated must first be
written into the FIFO. The smallest data element that
can be written into the FIFO is one byte.
the CRCGO bit.
The module incorporates a FIFO that is 8-level deep
when PLEN<3:0> > 7 and 16-deep, otherwise. The
data for which the CRC is to be calculated must first be
written into the FIFO. The smallest data element that
can be written into the FIFO is one byte.
For example, if PLEN = 5, then the size of the data is
PLEN + 1 = 6. The data must be written as follows:
PLEN + 1 = 6. The data must be written as follows:
data<5:0> = crc_input<5:0>
data<7:6> = bxx
data<7:6> = bxx
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of the VWORD bits
(CRCCON<12:8>) increments by one. The serial
shifter starts shifting data into the CRC engine when
CRCGO = 1 and VWORD<4:0> > 0. When the Most
Significant bit (MSb) is shifted out, the VWORD bits
decrement by one. The serial shifter continues shifting
until the VWORD bits reach zero. Therefore, for a given
value of PLEN, it will take (PLEN + 1) * VWORD
number of clock cycles to complete the CRC
calculations.
When the VWORD bits reach 8 (or 16), the CRCFUL bit
will be set. When the VWORD bits reach 0, the
CRCMPT bit will be set.
To continually feed data into the CRC engine, the
recommended mode of operation is to initially “prime”
the FIFO with a sufficient number of words so no
interrupt is generated before the next word can be
written. Once that is done, start the CRC by setting the
CRCGO bit to ‘1’. From that point onward, the VWORD
bits should be polled. If they read less than 8 or 16,
another word can be written into the FIFO.
defined by PLEN), the value of the VWORD bits
(CRCCON<12:8>) increments by one. The serial
shifter starts shifting data into the CRC engine when
CRCGO = 1 and VWORD<4:0> > 0. When the Most
Significant bit (MSb) is shifted out, the VWORD bits
decrement by one. The serial shifter continues shifting
until the VWORD bits reach zero. Therefore, for a given
value of PLEN, it will take (PLEN + 1) * VWORD
number of clock cycles to complete the CRC
calculations.
When the VWORD bits reach 8 (or 16), the CRCFUL bit
will be set. When the VWORD bits reach 0, the
CRCMPT bit will be set.
To continually feed data into the CRC engine, the
recommended mode of operation is to initially “prime”
the FIFO with a sufficient number of words so no
interrupt is generated before the next word can be
written. Once that is done, start the CRC by setting the
CRCGO bit to ‘1’. From that point onward, the VWORD
bits should be polled. If they read less than 8 or 16,
another word can be written into the FIFO.
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the
condition to generate an interrupt will not be met;
therefore, no interrupt will be generated (see
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the
condition to generate an interrupt will not be met;
therefore, no interrupt will be generated (see
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
CRCWDAT before a read of the VWORD bits is done.
20.1.2
INTERRUPT OPERATION
When the VWORD<4:0> bits make a transition from a
value of ‘1’ to ‘0’, an interrupt will be generated.
value of ‘1’ to ‘0’, an interrupt will be generated.
20.2
Operation in Power Save Modes
20.2.1
SLEEP MODE
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
the module will be suspended in its current state until
clock execution resumes.
20.2.2
IDLE MODE
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
D
Q
BIT 0
clk
D
Q
BIT 4
clk
D
Q
BIT 5
clk
D
Q
BIT 12
clk
XOR
SDOx
CRC Read Bus
CRC Write Bus
D
Q
BIT 15
clk