Microchip Technology MA240017 Data Sheet

 2008-2011 Microchip Technology Inc.

DS39927C-page 51

The data EEPROM memory is a Nonvolatile Memory
(NVM), separate from the program and volatile data
RAM. Data EEPROM memory is based on the same
Flash technology as program memory, and is optimized
for both long retention and a higher number of
erase/write cycles.
The data EEPROM is mapped to the top of the user
program memory space, with the top address at
program memory address, 7FFE00h to 7FFFFFh. The
size of the data EEPROM is 256 words in
PIC24F16KA102 devices. 
The data EEPROM is organized as 16-bit wide
memory. Each word is directly addressable, and is
readable and writable during normal operation over the
entire V

DD

 range.

Unlike the Flash program memory, normal program
execution is not stopped during a data EEPROM
program or erase operation.
The data EEPROM programming operations are
controlled using the three NVM Control registers:
• NVMCON: Nonvolatile Memory Control Register
• NVMKEY: Nonvolatile Memory Key Register 
• NVMADR: Nonvolatile Memory Address Register

The NVMCON register (

) is also the pri-

mary control register for data EEPROM program/erase
operations. The upper byte contains the control bits
used to start the program or erase cycle, and the flag
bit to indicate if the operation was successfully
performed. The lower byte of NVMCOM configures the
type of NVM operation that will be performed.

The NVMKEY is a write-only register that is used to
prevent accidental writes or erasures of data EEPROM
locations. 
To start any programming or erase sequence, the
following instructions must be executed first, in the
exact order provided:
1.

Write 55h to NVMKEY.

2.

Write AAh to NVMKEY.

After this sequence, a write will be allowed to the
NVMCON register for one instruction cycle. In most
cases, the user will simply need to set the WR bit in the
NVMCON register to start the program or erase cycle.
Interrupts should be disabled during the unlock
sequence.
The MPLAB

®

 C30 C compiler provides a defined library

procedure (builtin_write_NVM) to perform the
unlock sequence. 

illustrates how the

unlock sequence can be performed with in-line
assembly.

This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Data EEPROM, refer to the “PIC24F
Family Reference Manual”

,  Section 5.

 (DS39720).

//Disable Interrupts For 5 instructions 

asm volatile ("disi #5");

//Issue Unlock Sequence

asm volatile ("mov #0x55, W0

\n"

"mov W0, NVMKEY

\n"

"mov #0xAA, W1

\n"

"mov W1, NVMKEY

\n");

// Perform Write/Erase operations

asm volatile ("bset NVMCON, #WR   \n"

"nop

    \n"

"nop

\n");