Microchip Technology MA240017 Data Sheet
2008-2011 Microchip Technology Inc.
DS39927C-page 95
PIC24F16KA102 FAMILY
REGISTER 9-2:
CLKDIV: CLOCK DIVIDER REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
ROI
DOZE2
DOZE1
DOZE0
DOZEN
RCDIV2
RCDIV1
RCDIV0
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI:
Recover on Interrupt bit
1
= Interrupts clear the DOZEN bit and reset the CPU and peripheral clock ratio to 1:1
0
= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>:
CPU and Peripheral Clock Ratio Select bits
111
= 1:128
110
= 1:64
101
= 1:32
100
= 1:16
011
= 1:8
010
= 1:4
001
= 1:2
000
= 1:1
bit 11
DOZEN:
DOZE Enable bit
1
= DOZE<2:0> bits specify the CPU and peripheral clock ratio
0
= CPU and peripheral clock ratio are set to 1:1
bit 10-8
RCDIV<2:0>:
FRC Postscaler Select bits
When OSCCON (COSC<2:0>) = 111:
111
111
= 31.25 kHz (divide by 256)
110
= 125 kHz (divide by 64)
101
= 250 kHz (divide by 32)
100
= 500 kHz (divide by 16)
011
= 1 MHz (divide by 8)
010
= 2 MHz (divide by 4)
001
= 4 MHz (divide by 2) (default)
000
= 8 MHz (divide by 1)
When OSCCON (COSC<2:0>) = 110:
111
111
= 1.95 kHz (divide by 256)
110
= 7.81 kHz (divide by 64)
101
= 15.62 kHz (divide by 32)
100
= 31.25 kHz (divide by 16)
011
= 62.5 kHz (divide by 8)
010
= 125 kHz (divide by 4)
001
= 250 kHz (divide by 2) (default)
000
= 500 kHz (divide by 1)
bit 7-0
Unimplemented:
Read as ‘0’
Note 1:
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.