Microchip Technology MA240017 Data Sheet
PIC24F16KA102 FAMILY
DS39927C-page 98
2008-2011 Microchip Technology Inc.
The following code sequence for a clock switch is
recommended:
1.
recommended:
1.
Disable interrupts during the OSCCON register
unlock and write sequence.
unlock and write sequence.
2.
Execute the unlock sequence for the OSCCON
high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back instructions.
high byte by writing 78h and 9Ah to
OSCCON<15:8> in two back-to-back instructions.
3.
Write new oscillator source to the NOSCx bits in
the instruction immediately following the unlock
sequence.
the instruction immediately following the unlock
sequence.
4.
Execute the unlock sequence for the OSCCON
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
low byte by writing 46h and 57h to
OSCCON<7:0> in two back-to-back instructions.
5.
Set the OSWEN bit in the instruction immediately
following the unlock sequence.
following the unlock sequence.
6.
Continue to execute code that is not
clock-sensitive (optional).
clock-sensitive (optional).
7.
Invoke an appropriate amount of software delay
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
(cycle counting) to allow the selected oscillator
and/or PLL to start and stabilize.
8.
Check to see if OSWEN is ‘0’. If it is, the switch
was successful. If OSWEN is still set, then check
the LOCK bit to determine the cause of failure.
was successful. If OSWEN is still set, then check
the LOCK bit to determine the cause of failure.
The core sequence for unlocking the OSCCON register
and initiating a clock switch is provided in
and initiating a clock switch is provided in
EXAMPLE 9-1:
BASIC CODE SEQUENCE
FOR CLOCK SWITCHING
FOR CLOCK SWITCHING
9.5
Reference Clock Output
In addition to the CLKO output (F
OSC
/2) available in
certain oscillator modes, the device clock in the
PIC24F16KA102 family devices can also be configured
to provide a reference clock output signal to a port pin.
This feature is available in all oscillator configurations
and allows the user to select a greater range of clock
submultiples to drive external devices in the
application.
This reference clock output is controlled by the
REFOCON register (
PIC24F16KA102 family devices can also be configured
to provide a reference clock output signal to a port pin.
This feature is available in all oscillator configurations
and allows the user to select a greater range of clock
submultiples to drive external devices in the
application.
This reference clock output is controlled by the
REFOCON register (
). Setting the ROEN
bit (REFOCON<15>) makes the clock signal available
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the ROSEL bit is
not also set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
on the REFO pin. The RODIV bits (REFOCON<11:8>)
enable the selection of 16 different clock divider
options.
The ROSSLP and ROSEL bits (REFOCON<13:12>)
control the availability of the reference output during
Sleep mode. The ROSEL bit determines if the oscillator
on OSC1 and OSC2, or the current system clock
source, is used for the reference clock output. The
ROSSLP bit determines if the reference source is
available on REFO when the device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSSLP and ROSEL bits must be set. The device
clock must also be configured for one of the primary
modes (EC, HS or XT); otherwise, if the ROSEL bit is
not also set, the oscillator on OSC1 and OSC2 will be
powered down when the device enters Sleep mode.
Clearing the ROSEL bit allows the reference output
frequency to change as the system clock changes
during any clock switches.
;Place the new oscillator selection in W0
;OSCCONH (high byte) Unlock Sequence
MOV #OSCCONH,
w1
MOV #0x78,
w2
MOV #0x9A,
w3
MOV.b
w2, [w1]
MOV.b
w3, [w1]
;Set new oscillator selection
MOV.b WREG,
OSCCONH
;OSCCONL (low byte) unlock sequence
MOV #OSCCONL,
w1
MOV #0x46,
w2
MOV #0x57,
w3
MOV.b w2,
[w1]
MOV.b w3,
[w1]
;Start oscillator switch operation
BSET OSCCON,#0