Microchip Technology DM164130-2 Data Sheet
Conversion Factors
2012 Microchip Technology Inc.
DS41629A-page 57
EQUATION B-6:
The 256 factor in the numerator is the multiplier which scales the result up by one byte
width. Max Speed Request normalizes the constant to the speed request range. Notice
that Max Speed Request is 255, which is approximately equal to the 256 multiplier. The
difference is insignificant, so the 256 multiplier cancels out the Max Speed Request,
allowing the DUTY_CYCLE to be stored as an 8-bit integer.
width. Max Speed Request normalizes the constant to the speed request range. Notice
that Max Speed Request is 255, which is approximately equal to the 256 multiplier. The
difference is insignificant, so the 256 multiplier cancels out the Max Speed Request,
allowing the DUTY_CYCLE to be stored as an 8-bit integer.
B.7.2
SPEED_SCALING_CONST Constant
The SPEED_SCALING_CONST is used to convert the speed request to the number of
Timer1 counts in one commutation period. The SPEED_SCALING_CONST is a func-
tion of:
• Timer1 frequency
• Motor degrees per step
• Maximum speed request
• Maximum motor speed when the maximum drive voltage is applied
Timer1 counts in one commutation period. The SPEED_SCALING_CONST is a func-
tion of:
• Timer1 frequency
• Motor degrees per step
• Maximum speed request
• Maximum motor speed when the maximum drive voltage is applied
EQUATION B-7:
The SPEED_SCALING_CONST is stored as a 32-bit integer.
B.8
USTEP TABLE
In order to understand the microstep drive table values, you must first understand how
the PWM period duty cycle is generated: The output drive goes active at the beginning
of the PWM period, and is forced inactive part way through the period by the value of
a timer. The ratio of the active time relative to the PWM period is the duty cycle.
The PWM period is determined by the Timer2 frequency and PR2 register. Timer2
counts up to the value of PR2 then resets. The active drive period is determined by the
8-bit value in CCPR1L plus two more bits in CCP1CON. Two Least Significant bits of
Timer2 extend beyond the 8-bit Timer2 register (TMR2), and are used to compare with
the two CCP1CON bits mentioned. The CCP output drive is active from when Timer2
resets until the count reaches CCPR1L. The output drive remains inactive for the
remainder of the counts until Timer2 resets at the value of PR2.
The longest PWM period, for which there are 256 TMR2 counts, is achieved when PR2
is the maximum value. All 8 bits can be resolved for the duty cycle when PR2 is set to
the maximum. There are two additional Least Significant resolution bits in the
CCP1CON register, DCB0 and DCB1, which extend the duty cycle resolution to a max-
imum of 10 bits. Frequencies higher than the lowest require a PR2 value less than the
maximum. Anything less than the maximum value in PR2 will reduce the duty cycle res-
olution.
In our system, the PWM frequency is 16 kHz. The PR2 value to achieve this is 0x7D or
125 decimal. Actually, PR2 is set to 0x7C so that a 100% duty cycle is achieved when
0x7D is placed in the CCPR1L register. All values up to 0x7C can be expressed with 7
bits. Those 7 bits plus the two Least significant bits in the CCP1CON register yield a
9-bit duty cycle resolution. We use only the Most Significant 8 bits of the 9, because it
reduces the size and complexity of the microstepping look-up tables. Considering that
the maximum 7-bit PR2 value for 16 kHz operation is 125, then the 8-bit maximum
value (7 bits for CCPR1L and 1 bit for DCB1) is 250.
the PWM period duty cycle is generated: The output drive goes active at the beginning
of the PWM period, and is forced inactive part way through the period by the value of
a timer. The ratio of the active time relative to the PWM period is the duty cycle.
The PWM period is determined by the Timer2 frequency and PR2 register. Timer2
counts up to the value of PR2 then resets. The active drive period is determined by the
8-bit value in CCPR1L plus two more bits in CCP1CON. Two Least Significant bits of
Timer2 extend beyond the 8-bit Timer2 register (TMR2), and are used to compare with
the two CCP1CON bits mentioned. The CCP output drive is active from when Timer2
resets until the count reaches CCPR1L. The output drive remains inactive for the
remainder of the counts until Timer2 resets at the value of PR2.
The longest PWM period, for which there are 256 TMR2 counts, is achieved when PR2
is the maximum value. All 8 bits can be resolved for the duty cycle when PR2 is set to
the maximum. There are two additional Least Significant resolution bits in the
CCP1CON register, DCB0 and DCB1, which extend the duty cycle resolution to a max-
imum of 10 bits. Frequencies higher than the lowest require a PR2 value less than the
maximum. Anything less than the maximum value in PR2 will reduce the duty cycle res-
olution.
In our system, the PWM frequency is 16 kHz. The PR2 value to achieve this is 0x7D or
125 decimal. Actually, PR2 is set to 0x7C so that a 100% duty cycle is achieved when
0x7D is placed in the CCPR1L register. All values up to 0x7C can be expressed with 7
bits. Those 7 bits plus the two Least significant bits in the CCP1CON register yield a
9-bit duty cycle resolution. We use only the Most Significant 8 bits of the 9, because it
reduces the size and complexity of the microstepping look-up tables. Considering that
the maximum 7-bit PR2 value for 16 kHz operation is 125, then the 8-bit maximum
value (7 bits for CCPR1L and 1 bit for DCB1) is 250.
DUTY_CYCLE = (MAX_DUTY – MIN_DUTY + 1) * 256 / Max Speed Request
SPEED_SCALING_CONST = Timer 1 Frequency * Max Speed Request * Motor Degrees Per Step * 60 / 360 * Max RPM
SPEED_SCALING_CONST = Timer 1 Frequency * Motor Degrees Per Step * 255 / (6 * Max RPM)