Microchip Technology MA320002 Data Sheet

© 2011 Microchip Technology Inc.

DS61143H-page 203

• Updated the PIC32MX340F128H features in 

Table 1 to include 4 programmable DMA 
channels.

This revision includes minor typographical and
formatting changes throughout the data sheet text. 

Global changes include:

• Changed all instances of OSCI to OSC1 and 

OSCO to OSC2

• Changed all instances of V

DDCORE

 and 

V

DDCORE

/V

CAP

 to V

CAP

/V

DDCORE

• Deleted registers in most sections, refer to the 

related section of the “PIC32 Family Reference 
Manual” (DS61132).

The other changes are referenced by their respective
section in the following table.

Added a “Packages” column to Table 1 and Table 2.

Corrected all pin diagrams to update the following pin names.

• Changed PGC1/EMUC1 to PGEC1

• Changed PGD1/EMUD1 to PGED1

• Changed PGC2/EMUC2 to PGEC2

• Changed PGD2/EMUD2 to PGED2

Shaded appropriate pins in each diagram to indicate which pins are 5V tolerant.

Added 64-Lead QFN package pin diagrams, one for General Purpose and one 
for USB.

Reconstructed Figure 1-1 to include Timers, ADC and RTCC in the block 
diagram.

Added a new section to the data sheet that provides the following information:

• Basic Connection Requirements

• Capacitors

• Master Clear Pin

• ICSP™ Pins

• External Oscillator Pins

• Configuration of Analog and Digital Pins

• Unused I/Os

Updated the memory maps, Figure 4-1 through Figure 4-6.

All summary peripheral register maps were relocated to Section 4.0 “Memory 
Organization”.

Removed the “Address” column from Table 7-1.

Added a second paragraph in Section 12.1.3 “Analog Inputs” to clarify that all 
pins that share ANx functions are analog by default, because the AD1PCFG 
register has a default value of 0x0000.