Microchip Technology MA320002 Data Sheet

2011 Micr

och

ip T
e

chn

logy Inc.

1143H-p

age 57

PIC32MX3XX/4XX

TABLE 4-8:

INPUT CAPTURE1-5 REGISTERS MAP

irtual A

ddress

(BF80_#

)

Regis

ter

Bit Range

Bits

All

set

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

2000

IC1CON

(1)

31:16

—

0000

15:0

—

SIDL

—

FEDGE

C32

ICTMR

ICI<1:0>

ICOV

ICBNE

ICM<2:0>

0000

2010

IC1BUF

31:16

IC1BUF<31:0>

xxxx

15:0

xxxx

2200

IC2CON

(1)

31:16

—

0000

15:0

—

SIDL

—

FEDGE

C32

ICTMR

ICI<1:0>

ICOV

ICBNE

ICM<2:0>

0000

2210

IC2BUF

31:16

IC2BUF<31:0>

xxxx

15:0

xxxx

2400

IC3CON

(1)

31:16

—

0000

15:0

—

SIDL

—

FEDGE

C32

ICTMR

ICI<1:0>

ICOV

ICBNE

ICM<2:0>

0000

2410

IC3BUF

31:16

IC3BUF<31:0>

xxxx

15:0

xxxx

2600

IC4CON

(1)

31:16

—

0000

15:0

—

SIDL

—

FEDGE

C32

ICTMR

ICI<1:0>

ICOV

ICBNE

ICM<2:0>

0000

2610

IC4BUF

31:16

IC4BUF<31:0>

xxxx

15:0

xxxx

2800

IC5CON

(1)

31:16

—

0000

15:0

—

SIDL

—

FEDGE

C32

ICTMR

ICI<1:0>

ICOV

ICBNE

ICM<2:0>

0000

2810

IC5BUF

31:16

IC5BUF<31:0>

xxxx

15:0

xxxx

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more information.