Microchip Technology MA320002 Data Sheet

2011 Micr

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ip T
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logy Inc.

1143H-p

age 79

PIC32MX3XX/4XX

TABLE 4-39:

PREFETCH REGISTERS MAP

irtual Addr

8_#)

gist

Name

Bit Rang

Bits

All Re

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

4000 CHECON

(1)

31:16

—

CHECOH 0000

15:0

—

DCSZ<1:0>

—

PREFEN<1:0>

—

PFMWS<2:0>

0007

4010

CHEACC

(1)

31:16

CHEWEN

—

0000

15:0

—

CHEIDX<3:0>

00xx

4020

CHETAG

(1)

31:16 LTAGBOOT

—

LTAG<23:16>

xxx0

15:0

LTAG<15:4>

LVALID

LLOCK

LTYPE

—

xxx2

4030 CHEMSK

(1)

31:16

—

0000

15:0

LMASK<15:5>

—

xxxx

4040

CHEW0

31:16

CHEW0<31:0>

xxxx

15:0

xxxx

4050

CHEW1

31:16

CHEW1<31:0>

xxxx

15:0

xxxx

4060

CHEW2

31:16

CHEW2<31:0>

xxxx

15:0

xxxx

4070

CHEW3

31:16

CHEW3<31:0>

xxxx

15:0

xxxx

4080

CHELRU

31:16

—

CHELRU<24:16>

0000

15:0

CHELRU<15:0>

0000

4090

CHEHIT

31:16

CHEHIT<31:0>

xxxx

15:0

xxxx

40A0

CHEMIS

31:16

CHEMIS<31:0>

xxxx

15:0

xxxx

40C0 CHEPFABT

31:16

CHEPFABT<31:0>

xxxx

15:0

xxxx

Legend:

x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

Section 12.1.1 “CLR, SET and INV Registers”

for more information.