Microchip Technology AC164337 Data Sheet
2006-2014 Microchip Technology Inc.
DS70000178D-page 133
dsPIC30F1010/202X
12.23.1
FAULT INTERRUPTS
The FLTIENx bits in the PWMCONx registers deter-
mine if an interrupt will be generated when the FLTx
input is asserted high. The FLTMOD bits in the FCL-
CONx register determines how the PWM generator
and its outputs respond to the selected Fault input pin.
The FLTDAT<1:0> bits in the IOCONx registers supply
the data values to be assigned to the PWMxH,L pins in
the advent of a Fault.
mine if an interrupt will be generated when the FLTx
input is asserted high. The FLTMOD bits in the FCL-
CONx register determines how the PWM generator
and its outputs respond to the selected Fault input pin.
The FLTDAT<1:0> bits in the IOCONx registers supply
the data values to be assigned to the PWMxH,L pins in
the advent of a Fault.
The Fault pin logic can operate separately from the
PWM logic as an external interrupt pin. If the faults are
disabled from affecting the PWM generators in the
FCLCONx register, then the Fault pin can be used as a
general purpose interrupt pin.
PWM logic as an external interrupt pin. If the faults are
disabled from affecting the PWM generators in the
FCLCONx register, then the Fault pin can be used as a
general purpose interrupt pin.
12.23.2
FAULT STATES
The IOCONx register has two bits that determine the
state of each PWMx I/O pin when they are overridden
by a Fault input. When these bits are cleared, the
PWM I/O pin is driven to the inactive state. If the bit is
set, the PWM I/O pin is driven to the active state. The
active and inactive states are referenced to the polarity
defined for each PWM I/O pin (HPOL and LPOL
polarity control bits).
state of each PWMx I/O pin when they are overridden
by a Fault input. When these bits are cleared, the
PWM I/O pin is driven to the inactive state. If the bit is
set, the PWM I/O pin is driven to the active state. The
active and inactive states are referenced to the polarity
defined for each PWM I/O pin (HPOL and LPOL
polarity control bits).
12.23.3
FAULT INPUT MODES
The Fault input pin has two modes of operation:
• Latched Mode: When the Fault pin is asserted,
the PWM outputs go to the states defined in the
FLTDAT bits in the IOCONx registers. The PWM
outputs remain in this state until the Fault pin is
deasserted AND the corresponding interrupt flag
has been cleared in software. When both of these
actions have occurred, the PWM outputs return to
normal operation at the beginning of the next
PWM cycle boundary. If the FLTSTAT bit is
cleared before the Fault condition ends, the PWM
module waits until the Fault pin is no longer
asserted to restore the outputs. Software can
clear the FLTSTAT bit by writing a zero to the
FLTIEN bit.
FLTDAT bits in the IOCONx registers. The PWM
outputs remain in this state until the Fault pin is
deasserted AND the corresponding interrupt flag
has been cleared in software. When both of these
actions have occurred, the PWM outputs return to
normal operation at the beginning of the next
PWM cycle boundary. If the FLTSTAT bit is
cleared before the Fault condition ends, the PWM
module waits until the Fault pin is no longer
asserted to restore the outputs. Software can
clear the FLTSTAT bit by writing a zero to the
FLTIEN bit.
• Cycle-by-Cycle Mode: When the Fault input pin
is asserted, the PWM outputs remain in the deas-
serted PWM state for as long as the Fault pin is
asserted. For Complementary Output modes,
PWMH is low (deasserted) and PWML is high
(asserted). After the Fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle.
serted PWM state for as long as the Fault pin is
asserted. For Complementary Output modes,
PWMH is low (deasserted) and PWML is high
(asserted). After the Fault pin is driven high, the
PWM outputs return to normal operation at the
beginning of the following PWM cycle.
The operating mode for each Fault input pin is selected
using the FLTMOD<1:0> control bits in the FCLCONx
register.
using the FLTMOD<1:0> control bits in the FCLCONx
register.
12.23.4
FAULT ENTRY
The response of the PWM pins to the Fault input pins
is always asynchronous with respect to the device
clock signals. That is, the PWM outputs should imme-
diately go to the states defined in the FLTDAT register
bits without any interaction from the dsPIC DSC device
or software.
is always asynchronous with respect to the device
clock signals. That is, the PWM outputs should imme-
diately go to the states defined in the FLTDAT register
bits without any interaction from the dsPIC DSC device
or software.
Refer to Section 12.28 “Fault and Current-Limit
Override Issues with Dead-Time Logic” for informa-
tion regarding data sensitivity and behavior in response
to current-limit or Fault events.
Override Issues with Dead-Time Logic” for informa-
tion regarding data sensitivity and behavior in response
to current-limit or Fault events.
12.23.5
FAULT EXIT
The restoration of the PWM signals after a Fault condi-
tion has ended must occur at a PWM cycle boundary to
ensure proper synchronization of PWM signal edges
and manual signal overrides. The next PWM cycle
begins when the PTMRx value is zero.
tion has ended must occur at a PWM cycle boundary to
ensure proper synchronization of PWM signal edges
and manual signal overrides. The next PWM cycle
begins when the PTMRx value is zero.
12.23.6
FAULT EXIT WITH PTMR DISABLED
There is a special case for exiting a Fault condition
when the PWM time base is disabled (PTEN = 0).
When a Fault input is programmed for Cycle-by-Cycle
mode, the PWM outputs are immediately restored to
normal operation when the Fault input pin is deas-
serted. The PWM outputs should return to their default
programmed values. (The time base is disabled, so
there is no reason to wait for the beginning of the next
PWM cycle.)
when the PWM time base is disabled (PTEN = 0).
When a Fault input is programmed for Cycle-by-Cycle
mode, the PWM outputs are immediately restored to
normal operation when the Fault input pin is deas-
serted. The PWM outputs should return to their default
programmed values. (The time base is disabled, so
there is no reason to wait for the beginning of the next
PWM cycle.)
When a Fault input is programmed for Latched mode,
the PWM outputs are restored immediately when the
Fault input pin is deasserted AND the FSTAT bit has
been cleared in software.
the PWM outputs are restored immediately when the
Fault input pin is deasserted AND the FSTAT bit has
been cleared in software.
12.23.7
FAULT PIN SOFTWARE CONTROL
The Fault pin can be controlled manually in software.
Since the Fault input is shared with a PORT I/O pin, the
PORT pin can be configured as an output by clearing
the corresponding TRIS bit. When the PORT bit for the
pin is cleared, the Fault input will be activated.
Since the Fault input is shared with a PORT I/O pin, the
PORT pin can be configured as an output by clearing
the corresponding TRIS bit. When the PORT bit for the
pin is cleared, the Fault input will be activated.
Note:
The user should use caution when control-
ling the Fault inputs in software. If the
TRIS bit for the Fault pin is cleared and the
PORT bit is set high, then the Fault input
cannot be driven externally.
ling the Fault inputs in software. If the
TRIS bit for the Fault pin is cleared and the
PORT bit is set high, then the Fault input
cannot be driven externally.