Microchip Technology AC164337 Data Sheet
2006-2014 Microchip Technology Inc.
DS70000178D-page 185
dsPIC30F1010/202X
EXAMPLE 16-1:
ADC BASE REGISTER CODE (CONTINUED)
16.15 Changing A/D Clock
In general, the ADC cannot accept changes to the ADC
clock divisor while ADON = 1. If the user makes A/D
clock changes while ADON = 1, the results will be
indeterminate.
clock divisor while ADON = 1. If the user makes A/D
clock changes while ADON = 1, the results will be
indeterminate.
16.16 Sample and Conversion
The ADC module always assigns two ADC clock peri-
ods for the sampling process. When operating at the
maximum conversion rate of 2 Msps per channel, the
sampling period is:
ods for the sampling process. When operating at the
maximum conversion rate of 2 Msps per channel, the
sampling period is:
2 x 41.6 nsec = 83.3 nsec.
Each ADC pair specified in the ADCPCx registers initi-
ates a sample operation when the selected trigger
event occurs. The conversion of the sampled analog
data occurs as resources become available.
ates a sample operation when the selected trigger
event occurs. The conversion of the sampled analog
data occurs as resources become available.
If a new trigger event occurs for a specific channel
before a previous sample and convert request for that
channel has been processed, the newer request is
ignored. It is the user’s responsibility not to exceed the
conversion rate capability for the module.
before a previous sample and convert request for that
channel has been processed, the newer request is
ignored. It is the user’s responsibility not to exceed the
conversion rate capability for the module.
The actual conversion process requires 10 additional
ADC clocks. The conversion is processed serially, bit 9
first, then bit 8, down to bit 0. The result is stored when
the conversion is completed.
ADC clocks. The conversion is processed serially, bit 9
first, then bit 8, down to bit 0. The result is stored when
the conversion is completed.
; The actual pair conversion interrupt handler
; Don't forget to pop the stack when done and return from interrupt
ADC_PAIR0_PROC:
...
; The ADC pair 0 conversion complete handler
POP.S
; Restore W0-W3 and SR registers
RETFIE
; Return from Interrupt
ADC_PAIR1_PROC:
...
; The ADC pair 1 conversion complete handler
POP.S
; Restore W0-W3 and SR registers
RETFIE
; Return from Interrupt
ADC_PAIR2_PROC:
...
; The ADC pair 2 conversion complete handler
POP.S
; Restore W0-W3 and SR registers
RETFIE
; Return from Interrupt
ADC_PAIR3_PROC:
...
; The ADC pair 3 conversion complete handler
POP.S
; Restore W0-W3 and SR registers
RETFIE
; Return from Interrupt
ADC_PAIR4_PROC:
...
; The ADC pair 4 conversion complete handler
POP.S
; Restore W0-W3 and SR registers
RETFIE
; Return from Interrupt
ADC_PAIR5_PROC:
...
; The ADC pair 5 conversion complete handler
POP.S
; Restore W0-W3 and SR registers
RETFIE
; Return from Interrupt