Microchip Technology AC164337 Data Sheet
2006-2014 Microchip Technology Inc.
DS70000178D-page 171
dsPIC30F1010/202X
REGISTER 16-1:
A/D CONTROL REGISTER (ADCON)
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
U-0
R/W-0
ADON
—
ADSIDL
—
—
GSWTRG
—
FORM
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-1
R/W-1
EIE
ORDER
SEQSAMP
—
—
ADCS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: A/D Operating Mode bit
1
= A/D converter module is operating
0
= A/D converter is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: Stop in Idle Mode bit
1
= Discontinue module operation when device enters Idle mode
0
= Continue module operation in Idle mode
bit 12-11
Unimplemented: Read as ‘0’
bit 10
GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e.,
this bit is not auto-clearing).
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e.,
this bit is not auto-clearing).
bit 9
Unimplemented: Read as ‘0’
bit 8
FORM: Data Output Format bit
1
= Fractional (D
OUT
= dddd dddd dd00 0000)
0
= Integer (D
OUT
= 0000 00dd dddd dddd)
bit 7
EIE: Early Interrupt Enable bit
1
= Interrupt is generated after first conversion is completed
0
= Interrupt is generated after second conversion is completed
Note:
This control bit can only be changed while ADC is disabled (ADON = 0).
bit 6
ORDER: Conversion Order bit
1
= Odd numbered analog input is converted first, followed by conversion of even numbered input
0
= Even numbered analog input is converted first, followed by conversion of odd numbered input
Note:
This control bit can only be changed while ADC is disabled (ADON = 0).
bit 5
SEQSAMP: Sequential Sample Enable.
1
1
= Shared S&H is sampled at the start of the second conversion if ORDER = 0. If ORDER = 1, then
the shared S&H is sampled at the start of the first conversion.
0
= Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not
currently busy with an existing conversion process. If the shared S&H is busy at the time the
dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion
cycle
dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion
cycle
bit 4-3
Unimplemented: Read as ‘0’