Microchip Technology MA330031-2 Data Sheet

 2011-2013 Microchip Technology Inc.

DS70000657H-page 105

4.4.1

PAGED MEMORY SCHEME

The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X architecture
extends the available Data Space through a paging
scheme, which allows the available Data Space to
be accessed using MOV instructions in a linear
fashion for pre-modified and post-modified Effective
Addresses (EA). The upper half of the base Data
Space address is used in conjunction with the Data
Space Page registers, the 10-bit Read Page register
(DSRPAG) or the 9-bit Write Page register
(DSWPAG), to form an Extended Data Space (EDS)

address or Program Space Visibility (PSV) address.
The Data Space Page registers are located in the
SFR space.
Construction of the EDS address is shown in

. When DSRPAG<9> = 0 and the base

address bit, EA<15> = 1, the DSRPAG<8:0> bits are
concatenated onto EA<14:0> to form the 24-bit EDS
read address. Similarly, when base address bit,
EA<15> = 1, DSWPAG<8:0> are concatenated onto
EA<14:0> to form the 24-bit EDS write address.

1

DSRPAG<8:0>

9 Bits

EA

15 Bits

Select

Byte

24-Bit EDS EA

Select

EA

(DSRPAG = Don’t care)

No EDS Access

Select

16-Bit DS EA

Byte

EA<15> = 0

DSRPAG

0

EA<15>

 DS read access when DSRPAG = 0x000 will force an address error trap. 

= 1?

DSRPAG<9>

Y

N

Generate

PSV Address

0