Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 112
2011-2013 Microchip Technology Inc.
4.5
Instruction Addressing Modes
form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
4.5.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV
(f) to directly address data present in the first
8192 bytes of data memory (Near Data Space). Most
file register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV
instruction allows additional flexibility and can
access the entire Data Space.
4.5.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W reg-
ister fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W reg-
ister fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
TABLE 4-63:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Note:
Not all instructions support all the
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn form the Effective Address (EA).
Register Indirect Post-Modified
The contents of Wn form the EA. Wn is post-modified (incremented
or decremented) by a constant value.
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
to form the EA.
Register Indirect with Register Offset
(Register Indexed)
(Register Indexed)
The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.