Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 121
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
REGISTER 5-1:
NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0
(
)
R/W-0
R/W-0
(
R/W-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
NVMSIDL
)
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
R/W-0
(
)
R/W-0
(
)
R/W-0
R/W-0
—
—
—
—
NVMOP3
(
)
NVMOP2
NVMOP1
NVMOP0
bit 7
bit 0
Legend:
SO = Settable Only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR:
Write Control bit
(
1
= Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0
= Program or erase operation is complete and inactive
bit 14
WREN:
Write Enable bit
(
1
= Enables Flash program/erase operations
0
= Inhibits Flash program/erase operations
bit 13
WRERR:
Write Sequence Error Flag bit
(
)
1
= An improper program or erase sequence attempt or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0
= The program or erase operation completed normally
bit 12
NVMSIDL:
NVM Stop in Idle Control bit
(
)
1
= Flash voltage regulator goes into Standby mode during Idle mode
0
= Flash voltage regulator is active during Idle mode
bit 11-4
Unimplemented:
Read as ‘0’
bit 3-0
NVMOP<3:0>:
NVM Operation Select bits
,
1111
= Reserved
1110
= Reserved
1101
= Reserved
1100
= Reserved
1011
= Reserved
1010
= Reserved
0011
= Memory page erase operation
0010
= Reserved
0001
= Memory double-word program operation
0000
= Reserved
Note 1:
These bits can only be reset on a POR.
2:
If this bit is set, there will be minimal power savings (I
IDLE
) and upon exiting Idle mode, there is a delay
(T
VREG
) before Flash memory becomes operational.
3:
All other combinations of NVMOP<3:0> are unimplemented.
4:
Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5:
Two adjacent words on a 4-word boundary are programmed during execution of this operation.