Microchip Technology MA330031-2 Data Sheet

Page of 530
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 14
 2011-2013 Microchip Technology Inc.
Pin Diagrams (Continued) 
44-Pin QFN
(1,2,3)
= Pins are up to 5V tolerant 
44 43 42 41 40 39 38 37 36 35
12 13 14 15 16 17 18 19 20 21
3
30
29
28
27
26
25
24
23
4
5
7
8
9
10
11
1
2
32
31
6
22
33
34
PIC24EPXXXGP204
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN8/C3IN1+/U1RTS/BCLK1/RC2
V
DD
V
SS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
SDA2/RPI24/RA8
SCL2/RP36/RB4
TC
K/
C
V
RE
F
1O
/A
SCL
1/
R
P4
0
/T4
CK/
R
B8
RP
39
/INT
0/RB
7
PG
EC2
/AS
CL
2/
RP3
8/
R
B6
PG
ED2
/AS
DA2
/RP3
7/
RB5
V
DD
V
SS
SCL
1
/R
PI
53
/RC5
SDA1
/R
PI
5
2/
RC4
SCK1
/R
PI
5
1/
RC3
S
D
I1
/RP
I25
/RA
9
CV
RE
F
2O
/SDO1
/RP2
0/
T
1CK/
R
A
4
RPI45/CTPLS/RB13
RPI44/RB12
RP43/RB11
RP42/RB10
V
CAP
V
SS
RP57/RC9
RP56/RC8
RP55/RC7
RP54/RC6
TMS/ASDA1/RP41/RB9
(4)
TD
O
/R
A
10
T
D
I/RA
7
RPI4
6
/T
3
CK/RB1
4
RPI4
7
/T
5
CK/RB1
5
AV
SS
AV
DD
MC
LR
A
N
0/O
A
2OU
T
/R
A
0
AN1
/C2
IN
1+
/R
A1
PG
E
D
3/
V
RE
F
-/
A
N
2/C
2
IN
1-
/S
S
1
/RP
I32
/CT
E
D2/RB
0
PG
EC3
/V
RE
F
+/A
N
3/O
A
1
O
UT
/RP
I33
/CT
E
D1/RB
1
dsPIC33EPXXXGP504
Note
1:
The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See 
 for available peripherals and for information on limitations.
2:
Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See 
 for more information.
3:
The metal pad at the bottom of the device is not connected to any pins and is recommended to be connected 
to V
SS
 externally.
4:
There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the 
JTAGEN bit field in