Microchip Technology MA330031-2 Data Sheet

 2011-2013 Microchip Technology Inc.

DS70000657H-page 165

The preferred strategies for reducing power consumption
are changing clock speed and invoking one of the power-
saving modes. In some circumstances, this cannot be
practical. For example, it may be necessary for an
application to maintain uninterrupted synchronous
communication, even while it is doing nothing else.
Reducing system clock speed can introduce
communication errors, while using a power-saving mode
can stop communications completely.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate. 
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible configu-
rations, from 1:1 to 1:128, with 1:1 being the default
setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the ECAN™ module has been configured
for 500 kbps, based on this device operating speed. If
the device is placed in Doze mode with a clock fre-
quency ratio of 1:4, the ECAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.

The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid. 
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC

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variant. If the peripheral is present in the device, it is
enabled in the PMD register by default. 

Many useful resources are provided on the main prod-
uct page of the Microchip web site for the devices listed
in this data sheet. This product page, which can be
accessed using this 

, contains the latest updates

and additional information.

10.5.1

KEY RESOURCES

• “Watchdog Timer and Power-Saving Modes” 

(DS70615) in the “dsPIC33/PIC24 Family 
Reference Manual”

 

• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference 

 Sections

• Development Tools

If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable
module operation).

In the event you are not able to access the
product page using the link above, enter
this URL in your browser: