Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 203
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
12.0
TIMER1
The Timer1 module is a 16-bit timer that can operate as
a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated in Asynchronous Counter mode
a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated in Asynchronous Counter mode
from an external clock source
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and the
clock synchronization is performed after the prescaler
clock synchronization is performed after the prescaler
.
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (F
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (F
CY
).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
the input clock is derived from the external clock input
at the T1CK pin.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
T1CON<2>
• Timer Gate Control bit (TGATE): T1CON<6>
Timer control bit setting for different operating modes
are given in the
Timer control bit setting for different operating modes
are given in the
.
TABLE 12-1:
TIMER MODE SETTINGS
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note 1:
This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Timers” (DS70362) in the
“dsPIC33/PIC24 Family Reference Man-
ual
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Timers” (DS70362) in the
“dsPIC33/PIC24 Family Reference Man-
ual
”, which is available from the Microchip
www.microchip.com
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Mode
TCS
TGATE
TSYNC
Timer
0
0
x
Gated Timer
0
1
x
Synchronous
Counter
Counter
1
x
1
Asynchronous
Counter
Counter
1
x
0
TGATE
TCS
00
10
x1
PR1
TGATE
Set T1IF Flag
0
1
TSYNC
1
0
Sync
Equal
Reset
T1CK
Prescaler
(/n)
TCKPS<1:0>
Gate
Sync
Sync
F
P(1)
Falling Edge
Detect
TCKPS<1:0>
Note
1:
F
P
is the peripheral clock.
Latch
Data
CLK
T1CLK
CTMU
Edge Control
Logic
TMR1
Comparator
Prescaler
(/n)