Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 207
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
13.0
TIMER2/3 AND TIMER4/5
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent
16-bit timers with selectable operating modes.
As 32-bit timers, Timer2/3 and Timer4/5 operate in
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
which can also be configured as four independent
16-bit timers with selectable operating modes.
As 32-bit timers, Timer2/3 and Timer4/5 operate in
three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with all 16-Bit Operating modes (except
Asynchronous Counter mode)
Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
• Single 32-Bit Synchronous Counter
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
Modules (Timer2 and Timer3 only)
• ADC1 Event Trigger (32-bit timer pairs, and
Timer3 and Timer5 only)
Individually, all four of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, and
T4CON, T5CON registers. T2CON and T4CON are
shown in generic form in
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, and
T4CON, T5CON registers. T2CON and T4CON are
shown in generic form in
. T3CON and
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word (lsw); Timer3 and Timer5
are the most significant word (msw) of the 32-bit timers.
are the least significant word (lsw); Timer3 and Timer5
are the most significant word (msw) of the 32-bit timers.
A block diagram for an example 32-bit timer pair (Tim-
er2/3 and Timer4/5) is shown in
er2/3 and Timer4/5) is shown in
.
Note 1:
This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Timers” (DS70362) of the
“dsPIC33/PIC24 Family Reference
Manual”
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Timers” (DS70362) of the
“dsPIC33/PIC24 Family Reference
Manual”
, which is available from the
Microchip web site (
www.microchip.com
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
Note:
Only Timer2, 3, 4 and 5 can trigger a DMA
data transfer.
data transfer.