Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 216
2011-2013 Microchip Technology Inc.
REGISTER 14-2:
ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
—
IC32
bit 15
bit 8
R/W-0
R/W/HS-0
U-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
ICTRIG
(
)
TRIGSTAT
—
SYNCSEL4
)
SYNCSEL3
)
SYNCSEL2
)
SYNCSEL1
SYNCSEL0
)
bit 7
bit 0
Legend:
HS = Hardware Settable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
Unimplemented:
Read as ‘0’
bit 8
IC32:
Input Capture 32-Bit Timer Mode Select bit (Cascade mode)
1
= Odd IC and Even IC form a single 32-bit input capture module
(
0
= Cascade module operation is disabled
bit 7
ICTRIG:
Input Capture Trigger Operation Select bit
)
1
= Input source used to trigger the input capture timer (Trigger mode)
0
= Input source used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
bit 6
TRIGSTAT:
Timer Trigger Status bit
(
1
= ICxTMR has been triggered and is running
0
= ICxTMR has not been triggered and is being held clear
bit 5
Unimplemented:
Read as ‘0’
Note 1:
The IC32 bit in both the Odd and Even IC must be set to enable Cascade mode.
2:
The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3:
This bit is set by the selected input source (selected by SYNCSEL<4:0> bits). It can be read, set and
cleared in software.
cleared in software.
4:
Do not use the ICx module as its own Sync or Trigger source.
5:
This option should only be selected as a trigger source and not as a synchronization source.
6:
Each Input Capture x (ICx) module has one PTG input source. See
for more information.
PTGO8 = IC1
PTGO9 = IC2
PTGO10 = IC3
PTGO11 = IC4
PTGO9 = IC2
PTGO10 = IC3
PTGO11 = IC4