Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 236
2011-2013 Microchip Technology Inc.
bit 7-6
DTC<1:0>:
Dead-Time Control bits
11
= Dead-Time Compensation mode
10
= Dead-time function is disabled
01
= Negative dead time is actively applied for Complementary Output mode
00
= Positive dead time is actively applied for all output modes
bit 5
DTCP:
Dead-Time Compensation Polarity bit
When Set to ‘1’:
If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.
If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
When Set to ‘0’:
If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened.
If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.
If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.
If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened.
When Set to ‘0’:
If DTCMPx = 0, PWMxH is shortened and PWMxL is lengthened.
If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened.
bit 4
Unimplemented:
Read as ‘0’
bit 3
MTBS:
Master Time Base Select bit
1
= PWM generator uses the secondary master time base for synchronization and as the clock source
for the PWM generation logic (if secondary time base is available)
0
= PWM generator uses the primary master time base for synchronization and as the clock source
for the PWM generation logic
bit 2
CAM:
Center-Aligned Mode Enable bit
(
,
)
1
= Center-Aligned mode is enabled
0
= Edge-Aligned mode is enabled
bit 1
XPRES:
External PWMx Reset Control bit
(
1
= Current-limit source resets the time base for this PWM generator if it is in Independent Time Base
mode
0
= External pins do not affect PWMx time base
bit 0
IUE:
Immediate Update Enable bit
(
)
1
= Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are immediate
0
= Updates to the active MDC/PDCx/DTRx/ALTDTRx/PHASEx registers are synchronized to the
PWMx period boundary
REGISTER 16-7:
PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
Note 1:
Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2:
These bits should not be changed after the PWMx is enabled (PTEN = 1).
3:
DTC<1:0> = 11 for DTCP to be effective; otherwise, DTCP is ignored.
4:
The Independent Time Base (ITB = 1) mode must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
CAM bit is ignored.
5:
To operate in External Period Reset mode, the ITB bit must be ‘1’ and the CLMOD bit in the FCLCONx
register must be ‘0’.
register must be ‘0’.