Microchip Technology MA330031-2 Data Sheet
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
DS70000657H-page 252
2011-2013 Microchip Technology Inc.
17.2
QEI Control Registers
REGISTER 17-1:
QEI1CON: QEI1 CONTROL REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
QEIEN
—
QEISIDL
PIMOD2
(
)
PIMOD1
(
)
PIMOD0
(
IMV1
IMV0
bit 15
bit 8
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
INTDIV2
(
)
INTDIV1
(
)
INTDIV0
(
)
CNTPOL
GATEN
CCM1
CCM0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
QEIEN:
Quadrature Encoder Interface Module Counter Enable bit
1
= Module counters are enabled
0
= Module counters are disabled, but SFRs can be read or written to
bit 14
Unimplemented:
Read as ‘0’
bit 13
QEISIDL:
QEI Stop in Idle Mode bit
1
= Discontinues module operation when device enters Idle mode
0
= Continues module operation in Idle mode
bit 12-10
PIMOD<2:0>:
Position Counter Initialization Mode Select bits
(
111
= Reserved
110
= Modulo Count mode for position counter
101
= Resets the position counter when the position counter equals QEI1GEC register
100
= Second index event after home event initializes position counter with contents of QEI1IC register
011
= First index event after home event initializes position counter with contents of QEI1IC register
010
= Next index input event initializes the position counter with contents of QEI1IC register
001
= Every index input event resets the position counter
000
= Index input event does not affect position counter
bit 9
IMV1:
Index Match Value for Phase B bit
1
= Phase B match occurs when QEB = 1
0
= Phase B match occurs when QEB = 0
bit 8
IMV0:
Index Match Value for Phase A bit
1
= Phase A match occurs when QEA = 1
0
= Phase A match occurs when QEA = 0
bit 7
Unimplemented:
Read as ‘0’
Note 1:
When CCM<1:0> = 10 or 11, all of the QEI counters operate as timers and the PIMOD<2:0> bits are
ignored.
ignored.
2:
When CCM<1:0> = 00, and QEA and QEB values match the Index Match Value (IMV), the POSCNTH
and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity
values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
and POSCNTL registers are reset. QEA/QEB signals used for the index match have swap and polarity
values applied, as determined by the SWPAB and QEAPOL/QEBPOL bits.
3:
The selected clock rate should be at least twice the expected maximum quadrature count rate.