Microchip Technology MA330031-2 Data Sheet
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PIC3
PIC3
3E
P
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X
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X
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P
5
0X
,
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s
P
IC33
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PX
X
X
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MC
20
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X/5
0
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AND P
IC24
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C
20
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DS7
0000657H-page 322
2011-20
13 M
ic
rochip
T
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chnology
In
c.
FIGURE 23-1:
ADC MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS
0
1
+
–
CMP1
/OA1
0x
10
11
V
REFL
V
REFL
V
REFL
+
–
CH0
0
1
V
REFL
AN0-ANx
OA1-OA3
CH0Sx
CH0Nx
CH123Nx
00000
11111
OPMODE
OPMODE
OPMODE
A
B
1
0
CH0SA<4:0>
(3)
CH0SB<4:0>
(3)
CH0Sx
CH0Nx
CH0NA
(3)
CH0NB
(3)
CSCNA
CH123Sx
CH123Nx
CH123SA
CH123SB
CH123NA<2:0>
CH123NB<2:0>
S&H1
Alternate Input
Selection
Channel Scan
This diagram depicts all of the available
ADC connection options to the four S&H
amplifiers, which are designated: CH0,
CH1, CH2 and CH3.
The ANx analog pins or op amp outputs
are connected to the CH0-CH3 amplifi-
ers through the multiplexers, controlled
by the SFR control bits, CH0Sx,
CHONx, CH123Sx and CH123Nx.
ADC connection options to the four S&H
amplifiers, which are designated: CH0,
CH1, CH2 and CH3.
The ANx analog pins or op amp outputs
are connected to the CH0-CH3 amplifi-
ers through the multiplexers, controlled
by the SFR control bits, CH0Sx,
CHONx, CH123Sx and CH123Nx.
A
B
A
B
A
B
+
–
CH1
+
–
CH2
+
–
CH3
0
1
CH123Sx
+
–
OA2
0
1
CH123Sx
0x
10
11
CH123Nx
0x
10
11
CH123Nx
+
–
OA3
(5)
CH123Sx
AN0/OA2OUT/RA0
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
PGEC3/V
REF
+/AN3/OA1OUT/RPI33/CTED1/RB1
AN9/RPI27/RA11
AN1/C2IN1+/RA1
AN10/RPI28/RA12
PGED3/V
REF
-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
AN8/C3IN1+/U1RTS/BCLK1/RC2
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1
AN11/C1IN2-/U1CTS/RC11
+
–
OA1
V
REF
+
(1)
AV
DD
AV
SS
V
REF
-
(1)
VCFG<2:0>
ADC1BUF0
(4)
ADC1BUF1
(4)
ADC1BUF2
(4)
ADC1BUFF
(4)
ADC1BUFE
(4)
From CTMU
Current Source (CTMUI)
CTMU Temp
S&H2
S&H3
S&H0
Note
1:
V
REF
+, V
REF
- inputs can be multiplexed with other analog inputs.
2:
Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
3:
These bits can be updated with Step commands from the PTG module. See
for more information.
4:
When ADDMAEN (AD1CON4<8>) = 1, enabling DMA, only ADC1BUF0 is used.
5:
OA3 is not available for 28-pin devices.
Open
ALTS
(MUXA/MUXB)
SAR ADC
V
REFH
V
REFL