Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 35
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
3.0
CPU
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X CPU has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for digital
signal processing. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
50X and PIC24EPXXXGP/MC20X CPU has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for digital
signal processing. The CPU has a 24-bit instruction
word with a variable length opcode field. The Program
Counter (PC) is 23 bits wide and addresses up to
4M x 24 bits of user program memory space.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
3.1
Registers
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/
50X and PIC24EPXXXGP/MC20X devices have six-
teen, 16-bit working registers in the programmer’s
model. Each of the working registers can act as a data,
address or address offset register. The 16th working
register (W15) operates as a Software Stack Pointer for
interrupts and calls.
50X and PIC24EPXXXGP/MC20X devices have six-
teen, 16-bit working registers in the programmer’s
model. Each of the working registers can act as a data,
address or address offset register. The 16th working
register (W15) operates as a Software Stack Pointer for
interrupts and calls.
3.2
Instruction Set
The instruction set for dsPIC33EPXXXGP50X and
dsPIC33EPXXXMC20X/50X devices has two classes of
instructions: the MCU class of instructions and the DSP
class of instructions. The instruction set for
PIC24EPXXXGP/MC20X devices has the MCU class of
instructions only and does not support DSP instructions.
These two instruction classes are seamlessly integrated
into the architecture and execute from a single execution
unit. The instruction set includes many addressing modes
and was designed for optimum C compiler efficiency.
dsPIC33EPXXXMC20X/50X devices has two classes of
instructions: the MCU class of instructions and the DSP
class of instructions. The instruction set for
PIC24EPXXXGP/MC20X devices has the MCU class of
instructions only and does not support DSP instructions.
These two instruction classes are seamlessly integrated
into the architecture and execute from a single execution
unit. The instruction set includes many addressing modes
and was designed for optimum C compiler efficiency.
3.3
Data Space Addressing
The base Data Space can be addressed as 64 Kbytes
(32K words).
The Data Space includes two ranges of memory,
referred to as X and Y data memory. Each memory
range is accessible through its own independent
Address Generation Unit (AGU). The MCU class of
instructions operates solely through the X memory
AGU, which accesses the entire memory map as one
linear Data Space. On dsPIC33EPXXXMC20X/50X
and dsPIC33EPXXXGP50X devices, certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y Data Spaces
have memory locations that are device-specific, and
are described further in the data memory maps in
(32K words).
The Data Space includes two ranges of memory,
referred to as X and Y data memory. Each memory
range is accessible through its own independent
Address Generation Unit (AGU). The MCU class of
instructions operates solely through the X memory
AGU, which accesses the entire memory map as one
linear Data Space. On dsPIC33EPXXXMC20X/50X
and dsPIC33EPXXXGP50X devices, certain DSP
instructions operate through the X and Y AGUs to
support dual operand reads, which splits the data
address space into two parts. The X and Y Data Spaces
have memory locations that are device-specific, and
are described further in the data memory maps in
The upper 32 Kbytes of the Data Space memory map
can optionally be mapped into Program Space (PS) at
any 32-Kbyte aligned program word boundary. The
Program-to-Data Space mapping feature, known as
Program Space Visibility (PSV), lets any instruction
access Program Space as if it were Data Space.
Moreover, the Base Data Space address is used in
conjunction with a Read or Write Page register (DSRPAG
or DSWPAG) to form an Extended Data Space (EDS)
address. The EDS can be addressed as 8M words or
16 Mbytes. Refer to the “Data Memory” (DS70595) and
“Program Memory”
can optionally be mapped into Program Space (PS) at
any 32-Kbyte aligned program word boundary. The
Program-to-Data Space mapping feature, known as
Program Space Visibility (PSV), lets any instruction
access Program Space as if it were Data Space.
Moreover, the Base Data Space address is used in
conjunction with a Read or Write Page register (DSRPAG
or DSWPAG) to form an Extended Data Space (EDS)
address. The EDS can be addressed as 8M words or
16 Mbytes. Refer to the “Data Memory” (DS70595) and
“Program Memory”
(DS70613) sections in the
“dsPIC33/PIC24 Family Reference Manual”
for more
details on EDS, PSV and table accesses.
On the dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices, overhead-free circular
buffers (Modulo Addressing) are supported in both X
and Y address spaces. The Modulo Addressing
removes the software boundary checking overhead for
DSP algorithms. The X AGU Circular Addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data re-ordering for radix-2 FFT
algorithms. PIC24EPXXXGP/MC20X devices do not
support Modulo and Bit-Reversed Addressing.
On the dsPIC33EPXXXMC20X/50X and
dsPIC33EPXXXGP50X devices, overhead-free circular
buffers (Modulo Addressing) are supported in both X
and Y address spaces. The Modulo Addressing
removes the software boundary checking overhead for
DSP algorithms. The X AGU Circular Addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data re-ordering for radix-2 FFT
algorithms. PIC24EPXXXGP/MC20X devices do not
support Modulo and Bit-Reversed Addressing.
3.4
Addressing Modes
The CPU supports these addressing modes:
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
Note 1:
This data sheet summarizes the
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “CPU” (DS70359) in the
“dsPIC33/PIC24 Family Reference
Manual
features of the dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X families of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “CPU” (DS70359) in the
“dsPIC33/PIC24 Family Reference
Manual
”, which is available from the
www.microchip.com
).
2:
Some registers and associated bits
described in this section may not be
available on all devices. Refer to
described in this section may not be
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.