Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 357
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
FIGURE 25-4:
USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM
FIGURE 25-5:
DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM
SELSRCA<3:0>
SELSRCB<3:0>
SELSRCC<3:0>
AND
CMxMSKCON
MU
X A
MAI
MBI
MCI
Comparator Output
To Digital
Signals
Filter
OR
Blanking
Blanking
Blanking
Signals
Signals
ANDI
MASK
“AND-OR” Function
HLMS
MU
X B
MU
X
C
Blanking
Logic
(CMxMSKCON<15)
(CMxMSKSRC<11:8)
(CMxMSKSRC<7:4)
(CMxMSKSRC<3:0>)
MBI
MCI
MAI
MBI
MCI
MAI
C
X
OUT
CFLTREN
Digital Filter
TxCLK
(1,2)
SYNCO1
(3)
F
P(4)
F
OSC(4)
CFSEL<2:0>
CFDIV
Note
1:
See the Type C Timer Block Diagram (
2:
See the Type B Timer Block Diagram (
).
3:
See the High-Speed PWMx Module Register Interconnection Diagram (
).
4:
See the Oscillator System Diagram (
From Blanking Logic
1xx
010
000
001
1
0
(CMxFLTR<6:4>)
(CMxFLTR<3>)