Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 41
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 7-5
IPL<2:0>:
CPU Interrupt Priority Level Status bits
(
,
111
= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110
= CPU Interrupt Priority Level is 6 (14)
101
= CPU Interrupt Priority Level is 5 (13)
100
= CPU Interrupt Priority Level is 4 (12)
011
= CPU Interrupt Priority Level is 3 (11)
010
= CPU Interrupt Priority Level is 2 (10)
001
= CPU Interrupt Priority Level is 1 (9)
000
= CPU Interrupt Priority Level is 0 (8)
bit 4
RA:
REPEAT Loop Active bit
1
= REPEAT loop in progress
0
= REPEAT loop not in progress
bit 3
N:
MCU ALU Negative bit
1
= Result was negative
0
= Result was non-negative (zero or positive)
bit 2
OV:
MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1
causes the sign bit to change state.
1
= Overflow occurred for signed arithmetic (in this arithmetic operation)
0
= No overflow occurred
bit 1
Z:
MCU ALU Zero bit
1
= An operation that affects the Z bit has set it at some time in the past
0
= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C:
MCU ALU Carry/Borrow bit
1
= A carry-out from the Most Significant bit of the result occurred
0
= No carry-out from the Most Significant bit of the result occurred
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
Note 1:
This bit is available on dsPIC33EPXXXMC20X/50X and dsPIC33EPXXXGP50X devices only.
2:
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3:
The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
4:
A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.