Microchip Technology MA330031-2 Data Sheet
2011-2013 Microchip Technology Inc.
DS70000657H-page 471
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
31.2
AC Characteristics and Timing
Parameters
Parameters
The information contained in this section defines
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X AC characteristics and
timing parameters for high-temperature devices.
However, all AC timing specifications in this section are
the same as those in
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X AC characteristics and
timing parameters for high-temperature devices.
However, all AC timing specifications in this section are
the same as those in
, with the exception of the
parameters listed in this section.
in
is the Industrial and Extended temperature
equivalent of
.
TABLE 31-9:
TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
TABLE 31-10: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
(unless otherwise stated)
Operating temperature
-40°C
T
A
+150°C
Operating voltage V
DD
range as described in
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature
(unless otherwise stated)
Operating temperature
-40°C
T
A
+150°C
Param
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
HOS53
D
CLK
CLKO Stability (Jitter)
-5
0.5
5
%
Measured over 100 ms
period
period
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks use this formula:
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks use this formula:
V
DD
/2
C
L
R
L
Pin
Pin
V
SS
V
SS
C
L
R
L
= 464
C
L
= 50 pF for all pins except OSC2
15 pF for OSC2 output
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
Peripheral Clock Jitter
D
CLK
F
OSC
Peripheral Bit Rate Clock
--------------------------------------------------------------
------------------------------------------------------------------------
=
For example: F
OSC
= 32 MHz, D
CLK
= 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz.
SPI SCK Jitter
D
CLK
32 MHz
2 MHz
--------------------
------------------------------
5%
16
----------
5%
4
--------
1.25%
=
=
=
=