Microchip Technology SW006022-2N Data Sheet
MPLAB
®
XC16 C Compiler User’s Guide
DS52071B-page 180
2012 Microchip Technology Inc.
11.5
INTERRUPT SERVICE ROUTINE CONTEXT SAVING
Interrupts, by their very nature, can occur at unpredictable times. Therefore, the
interrupted code must be able to resume with the same machine state that was present
when the interrupt occurred.
interrupted code must be able to resume with the same machine state that was present
when the interrupt occurred.
To properly handle a return from interrupt, the setup (prologue) code for an ISR function
automatically saves the compiler-managed working and special function registers on
the stack for later restoration at the end of the ISR. You can use the optional save
parameter of the interrupt attribute to specify additional variables and SFRs to be
saved and restored.
automatically saves the compiler-managed working and special function registers on
the stack for later restoration at the end of the ISR. You can use the optional save
parameter of the interrupt attribute to specify additional variables and SFRs to be
saved and restored.
In certain applications, it may be necessary to insert assembly statements into the ISR
immediately prior to the compiler-generated function prologue. For example, it may be
required that a semaphore be incremented immediately on entry to an interrupt service
routine. This can be done as follows:
immediately prior to the compiler-generated function prologue. For example, it may be
required that a semaphore be incremented immediately on entry to an interrupt service
routine. This can be done as follows:
void
_ _
attribute
_ _
((
__
interrupt
_ _
,
_ _
auto_psv
_ _
(
_ _
preprologue
_ _
("inc _semaphore")))) isr0(void);
The context switch leads to latency in interrupt code execution, as described in
Section 11.8.3 “Latency”.
Section 11.8.3 “Latency”.
11.6
NESTING INTERRUPTS
The 16-bit devices support nested interrupts. Since processor resources are saved on
the stack in an ISR, nested ISRs are coded in just the same way as non-nested ones.
Nested interrupts are enabled by clearing the NSTDIS (nested interrupt disable) bit in
the INTCON1 register. Note that this is the default condition as the 16-bit device comes
out of Reset with nested interrupts enabled. Each interrupt source is assigned a priority
in the Interrupt Priority Control registers (IPCn).
the stack in an ISR, nested ISRs are coded in just the same way as non-nested ones.
Nested interrupts are enabled by clearing the NSTDIS (nested interrupt disable) bit in
the INTCON1 register. Note that this is the default condition as the 16-bit device comes
out of Reset with nested interrupts enabled. Each interrupt source is assigned a priority
in the Interrupt Priority Control registers (IPCn).
An interrupt is vectored if the priority of the interrupt source is greater than the current
CPU priority level.
CPU priority level.