Microchip Technology SW006022-2N Data Sheet
Interrupts
2012 Microchip Technology Inc.
DS52071B-page 183
11.8.1.1
DEVELOPMENT ISSUES
Here are some examples of the issues that should be considered:
EXAMPLE 11-1:
bar
MUST MATCH
baz
When it is required that bar and baz match (i.e., are updated synchronously with each
other), there is a possible hazard if either bar or baz can be updated within a higher
priority interrupt expression. Here are some sample flow sequences:
other), there is a possible hazard if either bar or baz can be updated within a higher
priority interrupt expression. Here are some sample flow sequences:
1.
Safe:
read bar
read baz
perform operation
write back result to foo
read bar
read baz
perform operation
write back result to foo
2.
Unsafe:
read bar
interrupt modifies baz
read baz
perform operation
write back result to foo
read bar
interrupt modifies baz
read baz
perform operation
write back result to foo
3.
Safe:
read bar
read baz
interrupt modifies bar or baz
perform operation
write back result to foo
read bar
read baz
interrupt modifies bar or baz
perform operation
write back result to foo
The first is safe because any interrupt falls outside the boundaries of the expression.
The second is unsafe because the application demands that bar and baz be updated
synchronously with each other. The third is probably safe; foo will possibly have an old
value, but the value will be consistent with the data that was available at the start of the
expression.
The second is unsafe because the application demands that bar and baz be updated
synchronously with each other. The third is probably safe; foo will possibly have an old
value, but the value will be consistent with the data that was available at the start of the
expression.
EXAMPLE 11-2:
TYPE OF
foo
,
bar
AND
baz
Another variation depends upon the type of foo, bar and baz. The operations, “read
bar”, “read baz”, or “write back result to foo”, may not be atomic, depending upon the
architecture of the target processor. For example, dsPIC DSC devices can read or write
an 8-bit, 16-bit, or 32-bit quantity in 1 (atomic) instruction. But, a 32-bit quantity may
require two instructions depending upon instruction selection (which in turn will depend
upon optimization and memory model settings). Assume that the types are long and
the compiler is unable to choose atomic operations for accessing the data. Then the
access becomes:
bar”, “read baz”, or “write back result to foo”, may not be atomic, depending upon the
architecture of the target processor. For example, dsPIC DSC devices can read or write
an 8-bit, 16-bit, or 32-bit quantity in 1 (atomic) instruction. But, a 32-bit quantity may
require two instructions depending upon instruction selection (which in turn will depend
upon optimization and memory model settings). Assume that the types are long and
the compiler is unable to choose atomic operations for accessing the data. Then the
access becomes:
read lsw bar
read msw bar
read lsw baz
read msw baz
perform operation (on lsw and on msw)
perform operation
write back lsw result to foo
write back msw result to foo
read msw bar
read lsw baz
read msw baz
perform operation (on lsw and on msw)
perform operation
write back lsw result to foo
write back msw result to foo
Now there are more possibilities for an update of bar or baz to cause unexpected data.