Microchip Technology 25LC320A-I/MS Memory IC MSOP-8 25LC320A-I/MS Data Sheet
Product codes
25LC320A-I/MS
25AA320A/25LC320A
DS21828F-page 10
© 2009 Microchip Technology Inc.
2.5
Read Status Register Instruction
(RDSR)
(RDSR)
The Read Status Register instruction (RDSR) provides
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
access to the STATUS register. The STATUS register
may be read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
The Write-In-Process (WIP) bit indicates whether the
25XX320A is busy with a write operation. When set to
a ‘
25XX320A is busy with a write operation. When set to
a ‘
1
’, a write is in progress, when set to a ‘
0
’, no write
is in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘
of the write enable latch and is read-only. When set to
a ‘
1
’, the latch allows writes to the array, when set to a
‘
0
’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 2-3.
See Figure 2-6 for the RDSR timing sequence.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
7
6
5
4
3
2
1
0
W/R
–
–
–
W/R
W/R
R
R
WPEN
X
X
X
BP1
BP0
WEL
WIP
W/R = writable/readable. R = read-only.
SO
SI
CS
9
10
11
12
13
14
15
1
1
0
0
0
0
0
0
7
6
5
4
2
1
0
Instruction
Data from STATUS Register
High-Impedance
SCK
0
2
3
4
5
6
7
1
8
3