Microchip Technology MCP1630DM-DDBS1 Data Sheet

©

 2007 Microchip Technology Inc.

DS41211D-page 27

The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bit of the OSCCON
register.

3.6.1

SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.

• When the SCS bit of the OSCCON register = 

0

, 

the system clock source is determined by 
configuration of the FOSC<2:0> bits in the 
Configuration Word register (CONFIG).

• When the SCS bit of the OSCCON register = 

1

, 

the system clock source is chosen by the internal 
oscillator frequency selected by the IRCF<2:0> 
bits of the OSCCON register. After a Reset, the 
SCS bit of the OSCCON register is always 
cleared.

3.6.2

OSCILLATOR START-UP TIME-OUT 
STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCCON register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word register (CONFIG), or from the internal clock
source. In particular, OSTS indicates that the Oscillator
Start-up Timer (OST) has timed out for LP, XT or HS
modes.

Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.

This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.

When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 3.4.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.

3.7.1

TWO-SPEED START-UP MODE 
CONFIGURATION

Two-Speed Start-up mode is configured by the
following settings:

• IESO (of the Configuration Word register) = 

1

; 

Internal/External Switchover bit (Two-Speed 
Start-up mode enabled).

• SCS (of the OSCCON register) = 

0

.

• FOSC<2:0> bits in the Configuration Word 

register (CONFIG) configured for LP, XT or HS 
mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after 

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be
anything other than LP, XT or HS mode, then
Two-Speed Start-up is disabled. This is because the
external clock oscillator does not require any
stabilization time after POR or an exit from Sleep.

3.7.2

TWO-SPEED START-UP 
SEQUENCE

1.

Wake-up from Power-on Reset or Sleep.

2.

Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.

3.

OST enabled to count 1024 clock cycles.

4.

OST timed out, wait for falling edge of the
internal oscillator.

5.

OSTS is set.

6.

System clock held low until the next falling edge
of new clock (LP, XT or HS mode).

7.

System clock is switched to external clock
source.

Any automatic clock switch, which may
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS bit
of the OSCCON register. The user can
monitor the OSTS bit of the OSCCON
register to determine the current system
clock source.

Executing a 

SLEEP

 instruction will abort

the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.