Microchip Technology MCP1630DM-DDBS1 Data Sheet
©
2007 Microchip Technology Inc.
DS41211D-page 57
PIC12F683
8.9
Comparator Gating Timer1
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 6.0 “Timer1 Module with Gate Control” for
details.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
8.10
Synchronizing Comparator Output
to Timer1
to Timer1
The comparator output can be synchronized with
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See the Comparator Block Diagram (Figure 8-
2) and the Timer1 Block Diagram (Figure 6-1) for more
information.
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See the Comparator Block Diagram (Figure 8-
2) and the Timer1 Block Diagram (Figure 6-1) for more
information.
REGISTER 8-2:
CMCON1: COMPARATOR CONFIGURATION REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-0
—
—
—
—
—
—
T1GSS
CMSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-2
Unimplemented: Read as ‘
0
’
bit 1
T1GSS: Timer1 Gate Source Select bit
(1)
1
= Timer 1 Gate Source is T1G pin (pin should be configured as digital input)
0
= Timer 1 Gate Source is comparator output
bit 0
CMSYNC: Comparator Output Synchronization bit
(2)
1
= Output is synchronized with falling edge of Timer1 clock
0
= Output is asynchronous
Note 1:
Refer to Section 6.6 “Timer1 Gate”.
2:
Refer to Figure 8-2.