Microchip Technology MCP1630DM-DDBS1 Data Sheet
PIC12F683
DS41211D-page 62
©
2007 Microchip Technology Inc.
9.1.3
ADC V
OLTAGE REFERENCE
The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either V
of the positive voltage reference. The positive voltage
reference can be either V
DD
or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
connected to the ground reference.
9.1.4
CONVERSION CLOCK
The source of the conversion clock is software select-
able via the ADCS bits of the ANSEL register. There
are seven possible clock options:
able via the ADCS bits of the ANSEL register. There
are seven possible clock options:
• F
OSC
/2
• F
OSC
/4
• F
OSC
/8
• F
OSC
/16
• F
OSC
/32
• F
OSC
/64
• F
RC
(dedicated internal oscillator)
The time to complete one bit conversion is defined as
T
T
AD
. One full 10-bit conversion requires 11 T
AD
periods
as shown in Figure 9-2.
For correct conversion, the appropriate T
AD
specification
must be met. See A/D conversion requirements in
Section 15.0 “Electrical Specifications” for more
information. Table 9-1 gives examples of appropriate
ADC clock selections.
Section 15.0 “Electrical Specifications” for more
information. Table 9-1 gives examples of appropriate
ADC clock selections.
TABLE 9-1:
ADC CLOCK PERIOD (T
AD
) V
S
. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
FIGURE 9-2:
ANALOG-TO-DIGITAL CONVERSION T
AD
CYCLES
Note:
Unless using the F
RC
, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
ADC clock frequency, which may
adversely affect the ADC result.
ADC Clock Period (T
AD
)
Device Frequency (F
OSC
)
ADC Clock Source
ADCS<2:0>
20 MHz
8 MHz
4 MHz
1 MHz
F
OSC
/2
000
100 ns
(2)
250 ns
(2)
500 ns
(2)
2.0
μ
s
F
OSC
/4
100
200 ns
(2)
500 ns
(2)
1.0
μ
s
(2)
4.0
μ
s
F
OSC
/8
001
400 ns
(2)
1.0
μ
s
(2)
2.0
μ
s
8.0
μ
s
(3)
F
OSC
/16
101
800 ns
(2)
2.0
μ
s
4.0
μ
s
16.0
μ
s
(3)
F
OSC
/32
010
1.6
μ
s
4.0
μ
s
8.0
μ
s
(3)
32.0
μ
s
(3)
F
OSC
/64
110
3.2
μ
s
8.0
μ
s
(3)
16.0
μ
s
(3)
64.0
μ
s
(3)
F
RC
x11
2-6
μ
s
(1,4)
2-6
μ
s
(1,4)
2-6
μ
s
(1,4)
2-6
μ
s
(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1:
The F
RC
source has a typical T
AD
time of 4
μ
s for V
DD
> 3.0V.
2:
These values violate the minimum required T
AD
time.
3:
For faster conversion times, the selection of another clock source is recommended.
4:
When the device frequency is greater than 1 MHz, the F
RC
clock source is only recommended if the
conversion will be performed during Sleep.
T
AD
1 T
AD
2 T
AD
3 T
AD
4 T
AD
5 T
AD
6 T
AD
7 T
AD
8 T
AD
9
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
b9
b8
b7
b6
b5
b4
b3
b2
T
AD
10 T
AD
11
b1
b0
T
CY
to T
AD
Conversion Starts
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input