Microchip Technology MCP1630DM-DDBS1 Data Sheet
©
2007 Microchip Technology Inc.
DS41211D-page 93
PIC12F683
12.4.2
TIMER0 INTERRUPT
An overflow (FFh
→
00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing the T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
enabled/disabled by setting/clearing the T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
12.4.3
GPIO INTERRUPT
An input change on GPIO change sets the GPIF bit of
the INTCON register. The interrupt can be
enabled/disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
the INTCON register. The interrupt can be
enabled/disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
FIGURE 12-7:
INTERRUPT LOGIC
Note:
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
TMR1IF
TMR1IE
CMIF
CMIE
CMIE
T0IF
T0IE
T0IE
INTF
INTE
INTE
GPIF
GPIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
EEIE
EEIF
ADIF
ADIE
ADIE
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
TMR2IF
TMR2IE
TMR2IE
CCP1IF
CCP1IE
CCP1IE
OSFIF
OSFIE
OSFIE