Microchip Technology 93LC56BT-I/OT Memory IC SOT-23-6 93LC56BT-I/OT Data Sheet

Product codes
93LC56BT-I/OT
Page of 36
93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
DS21794G-page 10
 2003-2011 Microchip Technology Inc.
2.8
Write
The WRITE instruction is followed by 8 bits (if ORG is
low or A-version devices) or 16 bits (if ORG pin is high
or B-version devices) of data which are written into the
specified address. For 93AA56A/B/C and 93LC56A/B/C
devices, after the last data bit is clocked into DI, the
falling edge of CS initiates the self-timed auto-erase and
programming cycle. For 93C56A/B/C devices, the self-
timed auto-erase and programming cycle is initiated by
the rising edge of CLK on the last data bit.
The DO pin indicates the Ready/
Busy
 status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
). DO at logical ‘0’ indicates that programming
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been written with
the data specified and the device is ready for another
instruction.
FIGURE 2-8:
WRITE TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-9:
WRITE TIMING FOR 93C DEVICES
Note:
After the Write cycle is complete, issuing a
Start bit and then taking CS low will clear
the Ready/
Busy
 status from DO.
CS
CLK
DI
DO
1
0
1
A
N
•••
A0
Dx
•••
D0
Busy
Ready
High-Z
High-Z
T
WC
T
CSL
T
CZ
T
SV
CS
CLK
DI
DO
1
0
1
A
N
•••
A0
Dx
•••
D0
Busy
Ready
High-Z
High-Z
T
WC
T
CSL
T
CZ
T
SV