Microchip Technology DM240015 Data Sheet
2012-2013 Microchip Technology Inc.
DS30009312B-page 13
PIC24FJ128GC010 FAMILY
1.0
DEVICE OVERVIEW
This document contains device-specific information for
the following devices:
the following devices:
The PIC24FJ128GC010 family expands the capabilities
of the PIC24F family by adding a complete selection of
advanced analog peripherals to its existing digital fea-
tures. This combination, along with its ultra low-power
features, Direct Memory Access (DMA) for peripherals,
USB On-The-Go (OTG) and a built-in LCD controller
and driver, makes this family the new standard for
mixed-signal PIC
of the PIC24F family by adding a complete selection of
advanced analog peripherals to its existing digital fea-
tures. This combination, along with its ultra low-power
features, Direct Memory Access (DMA) for peripherals,
USB On-The-Go (OTG) and a built-in LCD controller
and driver, makes this family the new standard for
mixed-signal PIC
®
microcontrollers in one economical
and power-saving package.
1.1
Core Features
1.1.1
16-BIT ARCHITECTURE
Central to all PIC24F devices is the 16-bit modified
Harvard architecture, first introduced with Microchip’s
dsPIC
Harvard architecture, first introduced with Microchip’s
dsPIC
®
Digital Signal Controllers (DSCs). The PIC24F
CPU core offers a wide range of enhancements, such as:
• 16-bit data and 24-bit address paths with the
• 16-bit data and 24-bit address paths with the
ability to move information between data and
memory spaces
memory spaces
• Linear addressing of up to 12 Mbytes (program
space) and 32 Kbytes (data)
• A 16-element working register array with built-in
software stack support
• A 17 x 17 hardware multiplier with support for
integer math
• Hardware support for 32 by 16-bit division
• An instruction set that supports multiple
• An instruction set that supports multiple
addressing modes and is optimized for high-level
languages, such as ‘C’
languages, such as ‘C’
• Operational performance up to 16 MIPS
1.1.2
XLP POWER-SAVING TECHNOLOGY
The PIC24FJ128GC010 family of devices introduces a
greatly expanded range of power-saving operating
modes for the ultimate in power conservation. The new
modes include:
• Retention Sleep, with essential circuits being
greatly expanded range of power-saving operating
modes for the ultimate in power conservation. The new
modes include:
• Retention Sleep, with essential circuits being
powered from a separate low-voltage regulator
• Retention Deep Sleep, a lower power mode that
maintains data RAM for fast start-up
• Deep Sleep without RTCC, for the lowest possible
power consumption under software control
• V
BAT
mode (with or without RTCC), to continue
limited operation from a backup battery when V
DD
is removed
Many of these new low-power modes also support the
continuous operation of the low-power, on-chip
Real-Time Clock/Calendar (RTCC), making it possible
for an application to keep time while the device is
otherwise asleep.
Aside from these new features, PIC24FJ128GC010
family devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
continuous operation of the low-power, on-chip
Real-Time Clock/Calendar (RTCC), making it possible
for an application to keep time while the device is
otherwise asleep.
Aside from these new features, PIC24FJ128GC010
family devices also include all of the legacy power-saving
features of previous PIC24F microcontrollers, such as:
• On-the-Fly Clock Switching, allowing the selection
of a lower power clock during run time
• Doze Mode Operation, for maintaining peripheral
clock speed while slowing the CPU clock
• Instruction-Based Power-Saving Modes, for quick
invocation of Idle and the many Sleep modes.
1.1.3
OSCILLATOR OPTIONS AND
FEATURES
FEATURES
All of the devices in the PIC24FJ128GC010 family offer
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes
• Two External Clock modes
• A Phase Lock Loop (PLL) frequency multiplier,
five different oscillator options, allowing users a range
of choices in developing application hardware. These
include:
• Two Crystal modes
• Two External Clock modes
• A Phase Lock Loop (PLL) frequency multiplier,
which allows clock speeds of up to 32 MHz
• A Fast Internal Oscillator (FRC) – nominal 8 MHz
output, with multiple frequency divider options and
automatic frequency self-calibration during run
time
automatic frequency self-calibration during run
time
• A separate Low-Power Internal RC Oscillator
(LPRC) – 31 kHz nominal, for low-power,
timing-insensitive applications.
timing-insensitive applications.
The internal oscillator block also provides a stable
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter-
nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
reference source for the Fail-Safe Clock Monitor
(FSCM). This option constantly monitors the main clock
source against a reference signal provided by the inter-
nal oscillator and enables the controller to switch to the
internal oscillator, allowing for continued low-speed
operation or a safe application shutdown.
1.1.4
EASY MIGRATION
Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. This
extends the ability of applications to grow from the
relatively simple, to the powerful and complex, while
still selecting a Microchip device.
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve. This
extends the ability of applications to grow from the
relatively simple, to the powerful and complex, while
still selecting a Microchip device.
• PIC24FJ64GC006
• PIC24FJ128GC006
• PIC24FJ64GC010
• PIC24FJ128GC010